loadpatents
name:-0.028573989868164
name:-0.027485847473145
name:-0.0051109790802002
Hall; Ronald P. Patent Filings

Hall; Ronald P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hall; Ronald P..The latest application filed is for "virtual channel support using write table".

Company Profile
5.32.26
  • Hall; Ronald P. - Cedar Park TX
  • Hall; Ronald P. - Austin TX
  • Hall; Ronald P - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Virtual Channel Support Using Write Table
App 20220083369 - Snyder; Michael D. ;   et al.
2022-03-17
Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests
Grant 11,080,188 - Tong , et al. August 3, 2
2021-08-03
Fetch predition circuit for reducing power consumption in a processor
Grant 10,901,484 - Blasco , et al. January 26, 2
2021-01-26
Cache flush method and apparatus
Grant 10,552,323 - Hall , et al. Fe
2020-02-04
Reducing Power Consumption In A Processor
App 20190286218 - Blasco; Conrado ;   et al.
2019-09-19
Accessing memories in coherent and non-coherent domains in a computing system
Grant 10,402,326 - Hall , et al. Sep
2019-09-03
Reducing power consumption in a processor
Grant 10,241,557 - Blasco , et al.
2019-03-26
Immediate branch recode that handles aliasing
Grant 9,940,262 - Sundar , et al. April 10, 2
2018-04-10
Cache for patterns of instructions with multiple forward control transfers
Grant 9,632,791 - Al-Otoom , et al. April 25, 2
2017-04-25
Instruction loop buffer with tiered power savings
Grant 9,524,011 - Hall , et al. December 20, 2
2016-12-20
Mechanism for reducing cache power consumption using cache way prediction
Grant 9,311,098 - Hall , et al. April 12, 2
2016-04-12
Immediate Branch Recode That Handles Aliasing
App 20160085550 - Sundar; Shyam ;   et al.
2016-03-24
Instruction Loop Buffer With Tiered Power Savings
App 20150293577 - Hall; Ronald P. ;   et al.
2015-10-15
Cache For Patterns Of Instructions
App 20150205725 - Al-Otoom; Muawya M. ;   et al.
2015-07-23
Reducing Power Consumption In A Processor
App 20150169041 - Blasco; Conrado ;   et al.
2015-06-18
Hardware assist thread for increasing code parallelism
Grant 9,037,837 - Hall , et al. May 19, 2
2015-05-19
Obtaining and releasing hardware threads without hypervisor involvement
Grant 8,898,441 - Frazier , et al. November 25, 2
2014-11-25
Mechanism for Reducing Cache Power Consumption Using Cache Way Prediction
App 20140337605 - Hall; Ronald P. ;   et al.
2014-11-13
Obtaining and releasing hardware threads without hypervisor involvement
Grant 8,793,474 - Frazier , et al. July 29, 2
2014-07-29
Scaleable status tracking of multiple assist hardware threads
Grant 8,719,554 - Arndt , et al. May 6, 2
2014-05-06
Scaleable status tracking of multiple assist hardware threads
Grant 8,713,290 - Arndt , et al. April 29, 2
2014-04-29
Hardware assist thread for dynamic performance profiling
Grant 8,612,730 - Hall , et al. December 17, 2
2013-12-17
Scaleable Status Tracking Of Multiple Assist Hardware Threads
App 20130139168 - Arndt; Richard Louis ;   et al.
2013-05-30
Hardware assist thread for increasing code parallelism
Grant 8,423,750 - Hall , et al. April 16, 2
2013-04-16
Hardware Assist Thread for Increasing Code Parallelism
App 20120254594 - Hall; Ronald P. ;   et al.
2012-10-04
Obtaining And Releasing Hardware Threads Without Hypervisor Involvement
App 20120210102 - Frazier; Giles Roger ;   et al.
2012-08-16
Issue unit for placing a processor into a gradual slow mode of operation
Grant 8,200,946 - Abernathy , et al. June 12, 2
2012-06-12
Scaleable Status Tracking Of Multiple Assist Hardware Threads
App 20120072707 - Arndt; Richard Louis ;   et al.
2012-03-22
Obtaining And Releasing Hardware Threads Without Hypervisor Involvement
App 20120072705 - Frazier; Giles Roger ;   et al.
2012-03-22
Hardware Assist for Optimizing Code During Processing
App 20120005462 - Hall; Ronald P. ;   et al.
2012-01-05
Hardware Assist Thread For Dynamic Performance Profiling
App 20110302395 - Hall; Ronald P. ;   et al.
2011-12-08
Hardware Assist Thread for Increasing Code Parallelism
App 20110283095 - Hall; Ronald P. ;   et al.
2011-11-17
Handling data cache misses out-of-order for asynchronous pipelines
Grant 7,900,024 - Abernathy , et al. March 1, 2
2011-03-01
Scalable link stack control method with full support for speculative operations
Grant 7,900,027 - Hall , et al. March 1, 2
2011-03-01
Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition
Grant 7,818,544 - Abernathy , et al. October 19, 2
2010-10-19
Selectively engaging optional data reduction mechanisms for capturing trace data
Grant 7,653,848 - Abernathy , et al. January 26, 2
2010-01-26
Scalable Link Stack Control Method With Full Support For Speculative Operations
App 20090198959 - Hall; Ronald P. ;   et al.
2009-08-06
Method for data set replacement in 4-way or greater locking cache
Grant 7,558,921 - Hall , et al. July 7, 2
2009-07-07
Pseudo-LRU virtual counter for a locking cache
Grant 7,516,275 - DeMent , et al. April 7, 2
2009-04-07
Handling Data Cache Misses Out-of-Order for Asynchronous Pipelines
App 20090043995 - Abernathy; Christopher M. ;   et al.
2009-02-12
Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation
App 20090006820 - Abernathy; Christopher M. ;   et al.
2009-01-01
Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation
App 20090006817 - Abernathy; Christopher M. ;   et al.
2009-01-01
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
Grant 7,461,239 - Abernathy , et al. December 2, 2
2008-12-02
Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
Grant 7,437,539 - Abernathy , et al. October 14, 2
2008-10-14
Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
Grant 7,434,033 - Abernathy , et al. October 7, 2
2008-10-07
System and Method for Selectively Engaging Optional Data Reduction Mechanisms for Capturing Trace Data
App 20080016407 - Abernathy; Christopher M. ;   et al.
2008-01-17
System and Method for Streaming High Frequency Trace Data Off-Chip
App 20080016408 - Abernathy; Christopher M. ;   et al.
2008-01-17
Pseudo-lru Virtual Counter For A Locking Cache
App 20070250667 - DEMENT; JONATHAN JAMES ;   et al.
2007-10-25
System And Method For Placing A Processor Into A Gradual Slow Mode Of Operation
App 20070245350 - Abernathy; Christopher M. ;   et al.
2007-10-18
Issue Unit For Placing A Processor Into A Gradual Slow Mode Of Operation
App 20070245129 - Abernathy; Christopher M. ;   et al.
2007-10-18
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
App 20070180221 - Abernathy; Christopher M. ;   et al.
2007-08-02
Method for data set replacement in 4-way or greater locking cache
App 20070043906 - Hall; Ronald P. ;   et al.
2007-02-22

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