Hagemeyer; Peter
Patent Applications and Registrations
Patent applications and USPTO patent grants for Hagemeyer; Peter.The latest application filed is for "layer arrangement and memory arrangement".
- Hagemeyer; Peter - Dresden DE
| Patent | Date |
|---|---|
| Method for fabricating a layer arrangement, layer arrangement and memory arrangement Grant 7,713,810 - Hagemeyer , et al. May 11, 2 | 2010-05-11 |
| Flash memory cell with buried floating gate and method for operating such a flash memory cell Grant 7,064,377 - Hagemeyer , et al. June 20, 2 | 2006-06-20 |
| Layer arrangement and memory arrangement App 20060008959 - Hagemeyer; Peter ; et al. | 2006-01-12 |
| Flash memory cell with buried floating gate and method for operating such a flash memory cell App 20040228187 - Hagemeyer, Peter ; et al. | 2004-11-18 |
| Vertical transistor, memory arrangement and method for fabricating a vertical transistor Grant 6,768,166 - Hagemeyer July 27, 2 | 2004-07-27 |
| Vertical transistor, memory arrangement and method for fabricating a vertical transistor App 20030015755 - Hagemeyer, Peter | 2003-01-23 |
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