Guzowski; Matthew T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Guzowski; Matthew T..The latest application filed is for "selective boundary overlay insertion for hierarchical circuit design".

Company Profile

1.11.11

Guzowski; Matthew T. - Essex Junction VT
Guzowski; Matthew T. - Essex VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked via rivets in chip hotspots Grant 11,308,257 - Chidambarrao , et al. April 19, 2	2022-04-19
Selective boundary overlay insertion for hierarchical circuit design Grant 9,971,861 - Behnen , et al. May 15, 2	2018-05-15
Selective Boundary Overlay Insertion For Hierarchical Circuit Design App 20170228486 - Behnen; Erwin ; et al.	2017-08-10
Reducing color conflicts in triple patterning lithography Grant 9,158,885 - Gray , et al. October 13, 2	2015-10-13
Systems And Methods For Fixing Pin Mismatch In Layout Migration App 20140019931 - MCCULLEN; Kevin W. ; et al.	2014-01-16
Systems and methods for fixing pin mismatch in layout migration Grant 8,627,247 - McCullen , et al. January 7, 2	2014-01-07
Schematic-based Layout Migration App 20120233576 - Barrows; Geoffrey R. ; et al.	2012-09-13
Adaptive weighting method for layout optimization with multiple priorities Grant 7,895,562 - Gray , et al. February 22, 2	2011-02-22
Layout optimization using parameterized cells Grant 7,865,848 - Gernhoefer , et al. January 4, 2	2011-01-04
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design Grant 7,752,589 - Allen , et al. July 6, 2	2010-07-06
Context aware sub-circuit layout modification Grant 7,735,042 - Gray , et al. June 8, 2	2010-06-08
Independent migration of hierarchical designs with methods of finding and fixing opens during migration Grant 7,568,173 - Gernhoefer , et al. July 28, 2	2009-07-28
Adaptive Weighting Method For Layout Optimization With Multiple Priorities App 20090158223 - Gray; Michael S. ; et al.	2009-06-18
Layout Optimization Using Parameterized Cells App 20090064061 - Gernhoefer; Veit ; et al.	2009-03-05
Method for implementing overlay-based modification of VLSI design layout Grant 7,490,308 - Gonzalez , et al. February 10, 2	2009-02-10
Polygonal Area Design Rule Correction Method For Vlsi Layouts App 20090037850 - Gray; Michael S. ; et al.	2009-02-05
Context Aware Sub-circuit Layout Modification App 20090037851 - Gray; Michael S. ; et al.	2009-02-05
Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration App 20080313581 - Gernhoefer; Veit ; et al.	2008-12-18
Method, Apparatus, And Computer Program Product For Displaying And Modifying The Critical Area Of An Integrated Circuit Design. App 20080168414 - Allen; Robert J. ; et al.	2008-07-10
Method For Implementing Overlay-based Modification Of Vlsi Design Layout App 20070234260 - Gonzalez; Christopher J. ; et al.	2007-10-04

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