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Tracking modifications to a virtual machine image that occur during backup of the virtual machine
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Information handling system with immediate scheduling of load operations
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Method for flagging data modification during a virtual machine backup
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System for flagging data modification during a virtual machine backup
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Virtual Machine Backup
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Virtual Machine Backup
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Virtual Machine Backup
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Virtual machine backup
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Tracking modifications to a virtual machine image that occur during backup of the virtual machine
Grant 10,133,641 - Guthrie , et al. November 20, 2 | 2018-11-20 |
Virtual machine backup
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Dynamic detection and correction of incorrect lock and atomic update hint bits
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Virtual Machine Backup
App 20180074911 - GUTHRIE; GUY LYNN ; et al. | 2018-03-15 |
Virtual Machine Backup
App 20180067816 - GUTHRIE; GUY LYNN ; et al. | 2018-03-08 |
Tracking modifications to a virtual machine image that occur during backup of the virtual machine
Grant 9,886,350 - Guthrie , et al. February 6, 2 | 2018-02-06 |
Tracking modifications to a virtual machine image that occur during backup of the virtual machine
Grant 9,880,905 - Guthrie , et al. January 30, 2 | 2018-01-30 |
Techniques for logging addresses of high-availability data via a non-blocking channel
Grant 9,792,208 - Ghai , et al. October 17, 2 | 2017-10-17 |
Dynamic Detection And Correction Of Incorrect Lock And Atomic Update Hint Bits
App 20170068545 - Nowak; Benjamin Carter ; et al. | 2017-03-09 |
Dynamic Detection And Software Correction Of Incorrect Lock And Atomic Update Hint Bits
App 20160364332 - Nowak; Benjamin Carter ; et al. | 2016-12-15 |
Dynamic detection and software correction of incorrect lock and atomic update hint bits
Grant 9,514,046 - Nowak , et al. December 6, 2 | 2016-12-06 |
Cache configured to log addresses of high-availability data
Grant 9,471,491 - Ghai , et al. October 18, 2 | 2016-10-18 |
Logging addresses of high-availability data
Grant 9,430,382 - Ghai , et al. August 30, 2 | 2016-08-30 |
Virtual Machine Backup
App 20160217045 - GUTHRIE; GUY LYNN ; et al. | 2016-07-28 |
Virtual Machine Backup
App 20160210197 - GUTHRIE; GUY LYNN ; et al. | 2016-07-21 |
Virtual Machine Backup
App 20160170881 - GUTHRIE; GUY LYNN ; et al. | 2016-06-16 |
Virtual Machine Backup
App 20160154663 - GUTHRIE; GUY LYNN ; et al. | 2016-06-02 |
Cache configured to log addresses of high-availability data via a non-blocking channel
Grant 9,336,142 - Ghai , et al. May 10, 2 | 2016-05-10 |
Techniques for moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache
Grant 9,280,465 - Guthrie , et al. March 8, 2 | 2016-03-08 |
Moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache
Grant 9,274,952 - Guthrie , et al. March 1, 2 | 2016-03-01 |
Virtual machine failover
Grant 9,069,701 - Guthrie , et al. June 30, 2 | 2015-06-30 |
Techniques for Logging Addresses of High-Availability Data
App 20150127906 - Ghai; Sanjeev ; et al. | 2015-05-07 |
Techniques for Logging Addresses of High-Availability Data Via a Non-Blocking Channel
App 20150127910 - Ghai; Sanjeev ; et al. | 2015-05-07 |
Logging Addresses of High-Availability Data Via a Non-Blocking Channel
App 20150127908 - Ghai; Sanjeev ; et al. | 2015-05-07 |
Logging Addresses of High-Availability Data
App 20150127909 - Ghai; Sanjeev ; et al. | 2015-05-07 |
Techniques for Moving Checkpoint-Based High-Availability Log and Data Directly From a Producer Cache to a Consumer Cache
App 20150100731 - Guthrie; Guy Lynn ; et al. | 2015-04-09 |
Moving Checkpoint-Based High-Availability Log and Data Directly From a Producer Cache to a Consumer Cache
App 20150100732 - Guthrie; Guy Lynn ; et al. | 2015-04-09 |
Virtual Machine Failover
App 20140164709 - Guthrie; Guy Lynn ; et al. | 2014-06-12 |
Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
Grant 8,433,851 - Clark , et al. April 30, 2 | 2013-04-30 |
Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted
Grant 8,352,712 - Bell, Jr. , et al. January 8, 2 | 2013-01-08 |
Processor system and methods of triggering a block move using a system bus write command initiated by user code
Grant 8,281,075 - Arimilli , et al. October 2, 2 | 2012-10-02 |
Data processing system and method for efficient coherency communication utilizing coherency domain indicators
Grant 8,230,178 - Fields, Jr. , et al. July 24, 2 | 2012-07-24 |
Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline
Grant 8,230,117 - Daly, Jr. , et al. July 24, 2 | 2012-07-24 |
Data processing system and method for efficient coherency communication utilizing coherency domains
Grant 8,214,600 - Fields, Jr. , et al. July 3, 2 | 2012-07-03 |
Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow
Grant 8,195,880 - Gai , et al. June 5, 2 | 2012-06-05 |
Chaining multiple smaller store queue entries for more efficient store queue usage
Grant 8,166,246 - Guthrie , et al. April 24, 2 | 2012-04-24 |
Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow
Grant 8,140,765 - Gai , et al. March 20, 2 | 2012-03-20 |
Information handling system with immediate scheduling of load operations and fine-grained access to cache memory
Grant 8,140,756 - Gai , et al. March 20, 2 | 2012-03-20 |
Specifying an access hint for prefetching partial cache block data in a cache hierarchy
Grant 8,140,759 - Frey , et al. March 20, 2 | 2012-03-20 |
System bus structure for large L2 cache array topology with different latency domains
Grant 8,015,358 - Chung , et al. September 6, 2 | 2011-09-06 |
L2 cache controller with slice directory and unified cache structure
Grant 8,001,330 - Clark , et al. August 16, 2 | 2011-08-16 |
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
Grant 7,987,320 - Bell, Jr. , et al. July 26, 2 | 2011-07-26 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
Grant 7,849,298 - Arimilli , et al. December 7, 2 | 2010-12-07 |
Victim cache using direct intervention
Grant 7,827,354 - Clark , et al. November 2, 2 | 2010-11-02 |
Information Handling System With Immediate Scheduling Of Load Operations In A Dual-bank Cache With Single Dispatch Into Write/read Data Flow
App 20100268890 - Ghai; Sanjeev ; et al. | 2010-10-21 |
Specifying An Access Hint For Prefetching Partial Cache Block Data In A Cache Hierarchy
App 20100268886 - Frey; Bradly George ; et al. | 2010-10-21 |
Load Request Scheduling In A Cache Hierarchy
App 20100268882 - Cargnoni; Robert Alan ; et al. | 2010-10-21 |
Information Handling System With Immediate Scheduling Of Load Operations
App 20100268895 - Ghai; Sanjeev ; et al. | 2010-10-21 |
Information Handling System With Immediate Scheduling Of Load Operations In A Dual-bank Cache With Dual Dispatch Into Write/read Data Flow
App 20100268887 - Ghai; Sanjeev ; et al. | 2010-10-21 |
Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory
App 20100268883 - Ghai; Sanjeev ; et al. | 2010-10-21 |
Techniques For Write-after-write Ordering In A Coherency Managed Processor System That Employs A Command Pipeline
App 20100262720 - Daly, JR.; George William ; et al. | 2010-10-14 |
Techniques For Triggering A Block Move Using A System Bus Write Command Initiated By User Code
App 20100262735 - Arimilli; Lakshminarayana Baba ; et al. | 2010-10-14 |
System bus structure for large L2 cache array topology with different latency domains
Grant 7,793,048 - Chung , et al. September 7, 2 | 2010-09-07 |
Cache coherent I/O communication
Grant 7,783,842 - Arimilli , et al. August 24, 2 | 2010-08-24 |
Efficient coherency communication utilizing an IG coherency state
Grant 7,783,841 - Fields, Jr. , et al. August 24, 2 | 2010-08-24 |
L2 cache array topology for large cache with different latency domains
Grant 7,783,834 - Clark , et al. August 24, 2 | 2010-08-24 |
Data processing system and method for efficient coherency communication utilizing coherency domain indicators
Grant 7,774,555 - Fields, Jr. , et al. August 10, 2 | 2010-08-10 |
Cache member protection with partial make MRU allocation
Grant 7,689,777 - Bell, Jr. , et al. March 30, 2 | 2010-03-30 |
Multiprocessor system with retry-less TLBI protocol
Grant 7,617,378 - Arimilli , et al. November 10, 2 | 2009-11-10 |
Data processing system and method for efficient communication utilizing an Ig coherency state
Grant 7,584,329 - Fields, Jr. , et al. September 1, 2 | 2009-09-01 |
Method For Chaining Multiple Smaller Store Queue Entries For More Efficient Store Queue Usage
App 20090198867 - Guthrie; Guy Lynn ; et al. | 2009-08-06 |
Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States
App 20090157945 - Arimilli; Ravi Kumar ; et al. | 2009-06-18 |
Cache Mechanism And Method For Avoiding Cast Out On Bad Victim Select And Recycling Victim Select Operation
App 20090150617 - BELL, JR.; ROBERT H. ; et al. | 2009-06-11 |
Method for priority scheduling and priority dispatching of store conditional operations in a store queue
Grant 7,533,227 - Guthrie , et al. May 12, 2 | 2009-05-12 |
L2 Cache Controller With Slice Directory And Unified Cache Structure
App 20090083489 - Clark; Leo James ; et al. | 2009-03-26 |
Data processing system and method for efficient L3 cache directory management
Grant 7,500,065 - Guthrie , et al. March 3, 2 | 2009-03-03 |
Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing
App 20090049248 - Clark; Leo James ; et al. | 2009-02-19 |
System and method for completing full updates to entire cache lines stores with address-only bus operations
Grant 7,493,446 - Arimilli , et al. February 17, 2 | 2009-02-17 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
Grant 7,493,478 - Arimilli , et al. February 17, 2 | 2009-02-17 |
Data processing system and method for efficient L3 cache directory management
Grant 7,490,202 - Guthrie , et al. February 10, 2 | 2009-02-10 |
L2 cache controller with slice directory and unified cache structure
Grant 7,490,200 - Clark , et al. February 10, 2 | 2009-02-10 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
Grant 7,480,772 - Fields, Jr. , et al. January 20, 2 | 2009-01-20 |
System Bus Structure For Large L2 Cache Array Topology With Different Latency Domains
App 20090006758 - Chung; Vicente Enrique ; et al. | 2009-01-01 |
System Bus Structure For Large L2 Cache Array Topology With Different Latency Domains
App 20090006759 - Chung; Vicente Enrique ; et al. | 2009-01-01 |
Data processing system and method for handling castout collisions
Grant 7,469,322 - Ghai , et al. December 23, 2 | 2008-12-23 |
System bus structure for large L2 cache array topology with different latency domains
Grant 7,469,318 - Chung , et al. December 23, 2 | 2008-12-23 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
Grant 7,454,577 - Fields, Jr. , et al. November 18, 2 | 2008-11-18 |
Pipelining D States For Mru Steerage During Mru-lru Member Allocation
App 20080244187 - BELL; ROBERT H. ; et al. | 2008-10-02 |
Cache Member Protection With Partial Make Mru Allocation
App 20080177953 - BELL; ROBERT H. ; et al. | 2008-07-24 |
Pipelining D states for MRU steerage during MRU/LRU member allocation
Grant 7,401,189 - Bell, Jr. , et al. July 15, 2 | 2008-07-15 |
Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue
App 20080140936 - Guthrie; Guy Lynn ; et al. | 2008-06-12 |
Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue
App 20080140953 - Guthrie; Guy Lynn ; et al. | 2008-06-12 |
System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations
App 20080140943 - Arimilli; Ravi Kumar ; et al. | 2008-06-12 |
Data processing system and method for handling castout collisions
Grant 7,366,844 - Ghai , et al. April 29, 2 | 2008-04-29 |
L2 cache array topology for large cache with different latency domains
Grant 7,366,841 - Clark , et al. April 29, 2 | 2008-04-29 |
Data Processing System and Method for Efficient L3 Cache Directory Management
App 20080098177 - Guthrie; Guy Lynn ; et al. | 2008-04-24 |
Cache member protection with partial make MRU allocation
Grant 7,363,433 - Bell, Jr. , et al. April 22, 2 | 2008-04-22 |
Data Processing System and Method for Efficient L3 Cache Directory Management
App 20080091885 - Guthrie; Guy Lynn ; et al. | 2008-04-17 |
System and method for completing updates to entire cache lines with address-only bus operations
Grant 7,360,021 - Arimilli , et al. April 15, 2 | 2008-04-15 |
Method for priority scheduling and priority dispatching of store conditional operations in a store queue
Grant 7,360,041 - Guthrie , et al. April 15, 2 | 2008-04-15 |
L2 Cache Array Topology For Large Cache With Different Latency Domains
App 20080077740 - Clark; Leo James ; et al. | 2008-03-27 |
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
Grant 7,343,455 - Bell, Jr. , et al. March 11, 2 | 2008-03-11 |
Data Processing System And Method For Efficient Communication Utilizing An Ig Coherency State
App 20080052471 - FIELDS, JR.; JAMES STEPHEN ; et al. | 2008-02-28 |
Data processing system and method for efficient L3 cache directory management
Grant 7,337,280 - Guthrie , et al. February 26, 2 | 2008-02-26 |
Victim Cache Using Direct Intervention
App 20080046651 - Clark; Leo James ; et al. | 2008-02-21 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
App 20080040556 - Fields; James Stephen JR. ; et al. | 2008-02-14 |
Data Processing System And Method For Handling Castout Collisions
App 20080040557 - Ghai; Sanjeev ; et al. | 2008-02-14 |
Data Processing System And Method For Efficient Coherency Communication Utilizing Coherency Domain Indicators
App 20080028155 - FIELDS; JAMES STEPHEN JR. ; et al. | 2008-01-31 |
Half-good mode for large L2 cache array topology with different latency domains
Grant 7,308,537 - Fields, Jr. , et al. December 11, 2 | 2007-12-11 |
System bus read data transfers with data ordering control bits
Grant 7,308,536 - Arimilli , et al. December 11, 2 | 2007-12-11 |
Victim cache using direct intervention
Grant 7,305,522 - Clark , et al. December 4, 2 | 2007-12-04 |
Cache memory direct intervention
Grant 7,305,523 - Guthrie , et al. December 4, 2 | 2007-12-04 |
System and method of re-ordering store operations within a processor
Grant 7,284,102 - Guthrie , et al. October 16, 2 | 2007-10-16 |
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
Grant 7,284,097 - Dodson , et al. October 16, 2 | 2007-10-16 |
Cross partition sharing of state information
Grant 7,272,664 - Arimilli , et al. September 18, 2 | 2007-09-18 |
Cache directory array recovery mechanism to support special ECC stuck bit matrix
Grant 7,272,773 - Cargnoni , et al. September 18, 2 | 2007-09-18 |
Processor, data processing system and method for synchronizing access to data in shared memory
Grant 7,228,385 - Guthrie , et al. June 5, 2 | 2007-06-05 |
Processor, data processing system and method for synchronizing access to data in shared memory
Grant 7,200,717 - Guthrie , et al. April 3, 2 | 2007-04-03 |
Processor, data processing system and method for synchronzing access to data in shared memory
Grant 7,197,604 - Guthrie , et al. March 27, 2 | 2007-03-27 |
System and method of responding to a cache read error with a temporary cache directory column delete
App 20070022250 - Fields; James Stephen JR. ; et al. | 2007-01-25 |
Managing processor architected state upon an interrupt
Grant 7,117,319 - Arimilli , et al. October 3, 2 | 2006-10-03 |
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state
Grant 7,103,721 - Cargnoni , et al. September 5, 2 | 2006-09-05 |
Cache memory direct intervention
App 20060184743 - Guthrie; Guy Lynn ; et al. | 2006-08-17 |
Victim cache using direct intervention
App 20060184742 - Clark; Leo James ; et al. | 2006-08-17 |
Half-good mode for large L2 cache array topology with different latency domains
App 20060179230 - Fields; James Stephen JR. ; et al. | 2006-08-10 |
Data processing system and method for efficient coherency communication utilizing coherency domains
App 20060179243 - Fields; James Stephen JR. ; et al. | 2006-08-10 |
Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
App 20060179235 - Bell; Robert H. JR. ; et al. | 2006-08-10 |
Data processing system and method for efficient coherency communication utilizing coherency domain indicators
App 20060179246 - Fields; James Stephen JR. ; et al. | 2006-08-10 |
Data processing system and method for efficient L3 cache directory management
App 20060179250 - Guthrie; Guy Lynn ; et al. | 2006-08-10 |
Cache member protection with partial make MRU allocation
App 20060179234 - Bell; Robert H. JR. ; et al. | 2006-08-10 |
System and method of re-ordering store operations within a processor
App 20060179226 - Guthrie; Guy Lynn ; et al. | 2006-08-10 |
Data processing system and method for efficient communication utilizing an Ig coherency state
App 20060179247 - Fields; James Stephen JR. ; et al. | 2006-08-10 |
Data processing system and method for handling castout collisions
App 20060179242 - Ghai; Sanjeev ; et al. | 2006-08-10 |
L2 cache array topology for large cache with different latency domains
App 20060179223 - Clark; Leo James ; et al. | 2006-08-10 |
L2 cache controller with slice directory and unified cache structure
App 20060179229 - Clark; Leo James ; et al. | 2006-08-10 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
App 20060179245 - Fields; James Stephen JR. ; et al. | 2006-08-10 |
Pipelining D states for MRU steerage during MRU/LRU member allocation
App 20060179232 - Bell; Robert H. JR. ; et al. | 2006-08-10 |
Multiprocessor system supporting multiple outstanding TLBI operations per partition
Grant 7,073,043 - Arimilli , et al. July 4, 2 | 2006-07-04 |
Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
Grant 7,069,494 - Cargnoni , et al. June 27, 2 | 2006-06-27 |
Data cache scrub mechanism for large L2/L3 data cache structures
Grant 7,055,003 - Cargnoni , et al. May 30, 2 | 2006-05-30 |
Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability
Grant 7,055,002 - Cargnoni , et al. May 30, 2 | 2006-05-30 |
Data processing system providing hardware acceleration of input/output (I/O) communication
Grant 7,047,320 - Arimilli , et al. May 16, 2 | 2006-05-16 |
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems
Grant 7,039,832 - Arimilli , et al. May 2, 2 | 2006-05-02 |
Method for priority scheduling and priority dispatching of store conditional operations in a store queue
App 20060090035 - Guthrie; Guy Lynn ; et al. | 2006-04-27 |
Processor, data processing system and method for synchronzing access to data in shared memory
App 20060085605 - Guthrie; Guy Lynn ; et al. | 2006-04-20 |
Processor, data processing system and method for synchronizing access to data in shared memory
App 20060085604 - Guthrie; Guy Lynn ; et al. | 2006-04-20 |
Processor, data processing system and method for synchronzing access to data in shared memory
App 20060085603 - Guthrie; Guy Lynn ; et al. | 2006-04-20 |
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
Grant 6,996,679 - Cargnoni , et al. February 7, 2 | 2006-02-07 |
Dynamically managing saved processor soft states
Grant 6,983,347 - Arimilli , et al. January 3, 2 | 2006-01-03 |
Processor virtualization mechanism via an enhanced restoration of hard architected states
Grant 6,981,083 - Arimilli , et al. December 27, 2 | 2005-12-27 |
Acceleration of input/output (I/O) communication through improved address translation
Grant 6,976,148 - Arimilli , et al. December 13, 2 | 2005-12-13 |
Layered local cache with lower level cache optimizing allocation mechanism
Grant 6,970,976 - Arimilli , et al. November 29, 2 | 2005-11-29 |
Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted
App 20050251660 - Bell, Robert H. JR. ; et al. | 2005-11-10 |
Method for completing full cacheline stores with address-only bus operations
App 20050251623 - Arimilli, Ravi Kumar ; et al. | 2005-11-10 |
System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture
Grant 6,963,967 - Guthrie , et al. November 8, 2 | 2005-11-08 |
System and method for reducing contention in a multi-sectored cache
Grant 6,950,909 - Guthrie , et al. September 27, 2 | 2005-09-27 |
Asynchronous non-blocking snoop invalidation
Grant 6,944,721 - Arimilli , et al. September 13, 2 | 2005-09-13 |
System bus read data transfers with data ordering control bits
App 20050193174 - Arimilli, Ravi Kumar ; et al. | 2005-09-01 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system
Grant 6,910,062 - Arimilli , et al. June 21, 2 | 2005-06-21 |
Speculative execution of instructions and processes before completion of preceding barrier operations
Grant 6,880,073 - Arimilli , et al. April 12, 2 | 2005-04-12 |
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
App 20050071573 - Dodson, John Steven ; et al. | 2005-03-31 |
System bus read data transfers with data ordering control bits
Grant 6,874,063 - Arimilli , et al. March 29, 2 | 2005-03-29 |
Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response
Grant 6,848,003 - Arimilli , et al. January 25, 2 | 2005-01-25 |
Apparatus for imprecisely tracking cache line inclusivity of a higher level cache
Grant 6,826,655 - Arimilli , et al. November 30, 2 | 2004-11-30 |
Cache invalidation bus for a highly scalable shared cache memory hierarchy
Grant 6,826,654 - Arimilli , et al. November 30, 2 | 2004-11-30 |
Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem
Grant 6,823,471 - Arimilli , et al. November 23, 2 | 2004-11-23 |
Local invalidation buses for a highly scalable shared cache memory hierarchy
Grant 6,813,694 - Arimilli , et al. November 2, 2 | 2004-11-02 |
Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability
App 20040215885 - Cargnoni, Robert Alan ; et al. | 2004-10-28 |
System and method for reducing contention in a multi-sectored cache
App 20040215900 - Guthrie, Guy Lynn ; et al. | 2004-10-28 |
Multiprocessor system with retry-less TLBI protocol
App 20040215897 - Arimilli, Ravi Kumar ; et al. | 2004-10-28 |
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
App 20040215889 - Cargnoni, Robert Alan ; et al. | 2004-10-28 |
Data cache scrub mechanism for large L2/L3 data cache structures
App 20040215886 - Cargnoni, Robert Alan ; et al. | 2004-10-28 |
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state
App 20040215890 - Cargnoni, Robert Alan ; et al. | 2004-10-28 |
Multiprocessor system supporting multiple outstanding TLBI operations per partition
App 20040215898 - Arimilli, Ravi Kumar ; et al. | 2004-10-28 |
Cache directory array recovery mechanism to support special ECC stuck bit matrix
App 20040210799 - Cargnoni, Robert Alan ; et al. | 2004-10-21 |
Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
App 20040210814 - Cargnoni, Robert Alan ; et al. | 2004-10-21 |
Imprecise snooping based invalidation mechanism
Grant 6,801,984 - Arimilli , et al. October 5, 2 | 2004-10-05 |
High performance symmetric multiprocessing systems via super-coherent data mechanisms
Grant 6,785,774 - Arimilli , et al. August 31, 2 | 2004-08-31 |
Symmetric multiprocessor systems with an independent super-coherent cache directory
Grant 6,779,086 - Arimilli , et al. August 17, 2 | 2004-08-17 |
Hardware-enabled instruction tracing
App 20040139305 - Arimilli, Ravi Kumar ; et al. | 2004-07-15 |
Data processing system providing hardware acceleration of input/outpuit (I/O) communication
App 20040139246 - Arimilli, Ravi Kumar ; et al. | 2004-07-15 |
Acceleration of input/output (I/O) communication through improved address translation
App 20040139295 - Arimilli, Ravi Kumar ; et al. | 2004-07-15 |
Cache coherent I/O communication
App 20040139283 - Arimilli, Ravi Kumar ; et al. | 2004-07-15 |
High speed virtual instruction execution mechanism
App 20040139304 - Arimilli, Ravi Kumar ; et al. | 2004-07-15 |
High performance cache intervention mechanism for symmetric multiprocessor systems
Grant 6,763,433 - Arimilli , et al. July 13, 2 | 2004-07-13 |
Super-coherent multiprocessor system bus protocols
Grant 6,763,435 - Arimilli , et al. July 13, 2 | 2004-07-13 |
Data processing system and method for resolving a conflict between requests to modify a shared cache line
Grant 6,763,434 - Arimilli , et al. July 13, 2 | 2004-07-13 |
Dynamically managing saved processor soft states
App 20040111562 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Interrupt handler prediction method and system
App 20040111593 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Processor virtualization mechanism via an enhanced restoration of hard architected states
App 20040111548 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Cross partition sharing of state information
App 20040111552 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/ systems
App 20040111653 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
App 20040111591 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Managing processor architected state upon an interrupt
App 20040111572 - Arimilli, Ravi Kumar ; et al. | 2004-06-10 |
Multi-level multiprocessor speculation mechanism
Grant 6,748,518 - Guthrie , et al. June 8, 2 | 2004-06-08 |
Microprocessor reservation mechanism for a hashed address system
Grant 6,748,501 - Arimilli , et al. June 8, 2 | 2004-06-08 |
System and method for providing multiprocessor speculation within a speculative branch path
Grant 6,728,873 - Guthrie , et al. April 27, 2 | 2004-04-27 |
Mechanism for folding storage barrier operations in a multiprocessor system
Grant 6,725,340 - Guthrie , et al. April 20, 2 | 2004-04-20 |
High performance data processing system via cache victimization protocols
Grant 6,721,853 - Guthrie , et al. April 13, 2 | 2004-04-13 |
Enhanced cache management mechanism via an intelligent system bus monitor
Grant 6,721,856 - Arimilli , et al. April 13, 2 | 2004-04-13 |
Local invalidation buses for a highly scalable shared cache memory hierarchy
App 20040059871 - Arimilli, Ravi Kumar ; et al. | 2004-03-25 |
Dynamic hardware and software performance optimizations for super-coherent SMP systems
Grant 6,704,844 - Arimilli , et al. March 9, 2 | 2004-03-09 |
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
Grant 6,704,843 - Arimilli , et al. March 9, 2 | 2004-03-09 |
Cache invalidation bus for a highly scalable shared cache memory hierarchy
App 20040030833 - Arimilli, Ravi Kumar ; et al. | 2004-02-12 |
Asynchronous non-blocking snoop invalidation
App 20040030843 - Arimilli, Ravi Kumar ; et al. | 2004-02-12 |
Multiprocessor speculation mechanism via a barrier speculation flag
Grant 6,691,220 - Guthrie , et al. February 10, 2 | 2004-02-10 |
Multi-node data processing system having a non-hierarchical interconnect architecture
Grant 6,671,712 - Arimilli , et al. December 30, 2 | 2003-12-30 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache
Grant 6,662,275 - Arimilli , et al. December 9, 2 | 2003-12-09 |
Super-coherent data mechanisms for shared caches in a multiprocessing system
Grant 6,658,539 - Arimilli , et al. December 2, 2 | 2003-12-02 |
Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction
Grant 6,658,556 - Arimilli , et al. December 2, 2 | 2003-12-02 |
Symmetric multiprocessor address bus protocol with intra-cache line access information
Grant 6,631,450 - Arimilli , et al. October 7, 2 | 2003-10-07 |
Intelligent cache management mechanism via processor access sequence analysis
Grant 6,629,210 - Arimilli , et al. September 30, 2 | 2003-09-30 |
High speed lock acquisition mechanism with time parameterized cache coherency states
Grant 6,629,212 - Arimilli , et al. September 30, 2 | 2003-09-30 |
Cache coherency protocol permitting sharing of a locked data granule
Grant 6,629,209 - Arimilli , et al. September 30, 2 | 2003-09-30 |
Extended cache coherency protocol with a persistent "lock acquired" state
Grant 6,629,214 - Arimilli , et al. September 30, 2 | 2003-09-30 |
Multiprocessor speculation mechanism for efficiently managing multiple barrier operations
Grant 6,625,660 - Guthrie , et al. September 23, 2 | 2003-09-23 |
Extended cache coherency protocol with a modified store instruction lock release indicator
Grant 6,625,701 - Arimilli , et al. September 23, 2 | 2003-09-23 |
Mechanism for collapsing store misses in an SMP computer system
Grant 6,615,321 - Arimilli , et al. September 2, 2 | 2003-09-02 |
Store collapsing mechanism for SMP computer system
Grant 6,615,320 - Arimilli , et al. September 2, 2 | 2003-09-02 |
System and method for asynchronously overlapping storage barrier operations with old and new storage operations
Grant 6,609,192 - Guthrie , et al. August 19, 2 | 2003-08-19 |
Multiprocessor speculation mechanism with imprecise recycling of storage operations
Grant 6,606,702 - Guthrie , et al. August 12, 2 | 2003-08-12 |
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
Grant 6,601,144 - Arimilli , et al. July 29, 2 | 2003-07-29 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls
Grant 6,601,145 - Arimilli , et al. July 29, 2 | 2003-07-29 |
Data processing system with HSA (hashed storage architecture)
Grant 6,598,118 - Arimilli , et al. July 22, 2 | 2003-07-22 |
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response
Grant 6,591,307 - Arimilli , et al. July 8, 2 | 2003-07-08 |
Multiprocessor system bus protocol with group addresses, responses, and priorities
Grant 6,591,321 - Arimilli , et al. July 8, 2 | 2003-07-08 |
Multiprocessor computer system with sectored cache line mechanism for cache intervention
Grant 6,571,322 - Arimilli , et al. May 27, 2 | 2003-05-27 |
High performance symmetric multiprocessing systems via super-coherent data mechanisms
App 20030097529 - Arimilli, Ravi Kumar ; et al. | 2003-05-22 |
Dynamic hardware and software performance optimizations for super-coherent SMP systems
App 20030097531 - Arimilli, Ravi Kumar ; et al. | 2003-05-22 |
Super-coherent data mechanisms for shared caches in a multiprocessing system
App 20030097528 - Arimilli, Ravi Kumar ; et al. | 2003-05-22 |
Super-coherent multiprocessor system bus protocols
App 20030097530 - Arimilli, Ravi Kumar ; et al. | 2003-05-22 |
Symmetric multiprocessor systems with an independent super-coherent cache directory
App 20030093624 - Arimilli, Ravi Kumar ; et al. | 2003-05-15 |
Extended cache coherency protocol with a "lock released" state
Grant 6,549,989 - Arimilli , et al. April 15, 2 | 2003-04-15 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update
Grant 6,546,468 - Arimilli , et al. April 8, 2 | 2003-04-08 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system
App 20030033350 - Arimilli, Ravi Kumar ; et al. | 2003-02-13 |
Multi-node data processing system and communication protocol having a partial combined response
Grant 6,519,649 - Arimilli , et al. February 11, 2 | 2003-02-11 |
High performance data processing system via cache victimization protocols
App 20030005232 - Guthrie, Guy Lynn ; et al. | 2003-01-02 |
Imprecise snooping based invalidation mechanism
App 20030005236 - Arimilli, Ravi Kumar ; et al. | 2003-01-02 |
Method and system for clearing dependent speculations from a request queue
Grant 6,487,637 - Arimilli , et al. November 26, 2 | 2002-11-26 |
Cache index based system address bus
Grant 6,477,613 - Arimilli , et al. November 5, 2 | 2002-11-05 |
Programmable agent and method for managing prefetch queues
Grant 6,470,427 - Arimilli , et al. October 22, 2 | 2002-10-22 |
Processor assigning data to hardware partition based on selectable hash of data address
Grant 6,470,442 - Arimilli , et al. October 22, 2 | 2002-10-22 |
Layered local cache with lower level cache updating upper and lower level cache directories
Grant 6,463,507 - Arimilli , et al. October 8, 2 | 2002-10-08 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers
App 20020129209 - Arimilli, Ravi Kumar ; et al. | 2002-09-12 |
Data processing system and method for resolving a conflict between requests to modify a shared cache line
App 20020129211 - Arimilli, Ravi Kumar ; et al. | 2002-09-12 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls
App 20020129210 - Arimilli, Ravi Kumar ; et al. | 2002-09-12 |
Method for upper level cache victim selection management by a lower level cache
Grant 6,446,166 - Arimilli , et al. September 3, 2 | 2002-09-03 |
Method and system for cancelling speculative cache prefetch requests
Grant 6,438,656 - Arimilli , et al. August 20, 2 | 2002-08-20 |
Mechanism for collapsing store misses in an SMP computer system
App 20020112128 - Arimilli, Ravi Kumar ; et al. | 2002-08-15 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache
App 20020112129 - Arimilli, Ravi Kumar ; et al. | 2002-08-15 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache
App 20020112124 - Arimilli, Ravi Kumar ; et al. | 2002-08-15 |
Store collapsing mechanism for SMP computer system
App 20020112130 - Arimilli, Ravi Kumar ; et al. | 2002-08-15 |
Method and system for managing speculative requests in a multi-level memory hierarchy
Grant 6,418,516 - Arimilli , et al. July 9, 2 | 2002-07-09 |
Microprocessor reservation mechanism for a hashed address system
App 20020087815 - Arimilli, Ravi Kumar ; et al. | 2002-07-04 |
Multiprocessor computer system with sectored cache line system bus protocol mechanism
App 20020087791 - Arimilli, Ravi Kumar ; et al. | 2002-07-04 |
Multiprocessor computer system with sectored cache line mechanism for load and store operations
App 20020087792 - Arimilli, Ravi Kumar ; et al. | 2002-07-04 |
Multiprocessor computer system with sectored cache line mechanism for cache intervention
App 20020087809 - Arimilli, Ravi Kumar ; et al. | 2002-07-04 |
Full multiprocessor speculation mechanism in a symmetric multiprocessor (smp) System
App 20020087849 - Arimilli, Ravi Kumar ; et al. | 2002-07-04 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update
App 20020083268 - Arimilli, Ravi Kumar ; et al. | 2002-06-27 |
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response
Grant 6,405,289 - Arimilli , et al. June 11, 2 | 2002-06-11 |
Layered local cache mechanism with split register load bus and cache load bus
Grant 6,405,285 - Arimilli , et al. June 11, 2 | 2002-06-11 |
Cache memory having a programmable cache replacement scheme
Grant 6,397,298 - Arimilli , et al. May 28, 2 | 2002-05-28 |
High performance store instruction management via imprecise local cache update mechanism
Grant 6,397,300 - Arimilli , et al. May 28, 2 | 2002-05-28 |
Optimized cache allocation algorithm for multiple speculative requests
Grant 6,393,528 - Arimilli , et al. May 21, 2 | 2002-05-21 |
Extended cache state with prefetched stream ID information
Grant 6,360,299 - Arimilli , et al. March 19, 2 | 2002-03-19 |
Method and system for communication in which a castout operation is cancelled in response to snoop responses
Grant 6,349,367 - Arimilli , et al. February 19, 2 | 2002-02-19 |
Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line
Grant 6,345,342 - Arimilli , et al. February 5, 2 | 2002-02-05 |
Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction
Grant 6,343,347 - Arimilli , et al. January 29, 2 | 2002-01-29 |
System bus directory snooping mechanism for read/castout (RCO) address transaction
Grant 6,343,344 - Arimilli , et al. January 29, 2 | 2002-01-29 |
Ordering for pipelined read transfers
Grant 6,327,636 - Guthrie , et al. December 4, 2 | 2001-12-04 |
Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data
Grant 6,321,305 - Arimilli , et al. November 20, 2 | 2001-11-20 |
High performance multiprocessor system with modified-unsolicited cache state
Grant 6,321,306 - Arimilli , et al. November 20, 2 | 2001-11-20 |
Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position
Grant 6,279,086 - Arimilli , et al. August 21, 2 | 2001-08-21 |
Multiprocessor system bus with system controller explicitly updating snooper cache state information
Grant 6,275,909 - Arimilli , et al. August 14, 2 | 2001-08-14 |
High performance multichannel DMA controller for a PCI host bridge with a built-in cache
Grant 6,230,219 - Fields, Jr. , et al. May 8, 2 | 2001-05-08 |
Dual host bridge with peer to peer support
Grant 6,175,888 - Guthrie , et al. January 16, 2 | 2001-01-16 |
Configuration access system
Grant 6,101,563 - Fields, Jr. , et al. August 8, 2 | 2000-08-08 |
Method and apparatus of selecting data transmission channels
Grant 6,049,841 - Fields, Jr. , et al. April 11, 2 | 2000-04-11 |
Enhanced dual speed bus computer system
Grant 5,978,869 - Guthrie , et al. November 2, 1 | 1999-11-02 |
Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system
Grant 5,898,888 - Guthrie , et al. April 27, 1 | 1999-04-27 |
Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches
Grant 5,887,144 - Guthrie , et al. March 23, 1 | 1999-03-23 |
Data processing system having demand based write through cache with enforced ordering
Grant 5,796,979 - Arimilli , et al. August 18, 1 | 1998-08-18 |
Method and apparatus for adding and removing components of a data processing system without powering down
Grant 5,784,576 - Guthrie , et al. July 21, 1 | 1998-07-21 |
System and method for enhancement of system bus to mezzanine bus transactions
Grant 5,673,399 - Guthrie , et al. September 30, 1 | 1997-09-30 |
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