Gurram; Chandra

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gurram; Chandra.The latest application filed is for "systems and methods for reducing register bank conflicts based on software hint and hardware thread switch".

Company Profile

7.6.12

Gurram; Chandra - Folsom CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Grant 11,361,496 - Maiyuran , et al. June 14, 2	2022-06-14
Systems And Methods For Reducing Register Bank Conflicts Based On Software Hint And Hardware Thread Switch App 20220179655 - CHENG; BUQI ; et al.	2022-06-09
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays With Feedback Inputs App 20220156343 - MAIYURAN; SUBRAMANIAM ; et al.	2022-05-19
Graphics Processors And Graphics Processing Units Having Dot Product Accumulate Instruction For Hybrid Floating Point Format App 20220129266 - Maiyuran; Subramaniam ; et al.	2022-04-28
Computing Efficient Cross Channel Operations In Parallel Computing Machines Using Systolic Arrays App 20220058158 - Maiyuran; Subramaniam ; et al.	2022-02-24
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Grant 11,204,977 - Maiyuran , et al. December 21, 2	2021-12-21
Computing Efficient Cross Channel Operations In Parallel Computing Machines Using Systolic Arrays App 20210365402 - Maiyuran; Subramaniam ; et al.	2021-11-25
Computing efficient cross channel operations in parallel computing machines using systolic arrays Grant 11,182,337 - Maiyuran , et al. November 23, 2	2021-11-23
Compaction Of Diverged Lanes For Efficient Use Of Alus App 20210349717 - Gurram; Chandra ; et al.	2021-11-11
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays With Feedback Inputs App 20210349966 - MAIYURAN; SUBRAMANIAM ; et al.	2021-11-11
Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch Grant 11,163,578 - Cheng , et al. November 2, 2	2021-11-02
Graphics Processors And Graphics Processing Units Having Dot Product Accumulate Instruction For Hybrid Floating Point Format App 20210312697 - Maiyuran; Subramaniam ; et al.	2021-10-07
Resource load balancing based on usage and power limits Grant 10,983,581 - Jahagirdar , et al. April 20, 2	2021-04-20
Utilizing Structured Sparsity In Systolic Arrays App 20210081201 - Maiyuran; Subramaniam ; et al.	2021-03-18
Register bank conflict reduction for multi-threaded processor Grant 10,754,651 - Gurram , et al. A	2020-08-25
Register Bank Conflict Reduction For Multi-threaded Processor App 20200004534 - Gurram; Chandra ; et al.	2020-01-02
Systems And Methods For Reducing Register Bank Conflicts Based On Software Hint And Hardware Thread Switch App 20190265974 - CHENG; BUQI ; et al.	2019-08-29
Resource Load Balancing Based On Usage And Power Limits App 20190204894 - Jahagirdar; Sanjeev ; et al.	2019-07-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.