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High-speed Multi-port Memory Supporting Collision
App 20220310156 - RAJ; Pradeep ; et al. | 2022-09-29 |
Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memories
App 20220293148 - Bhaskaran; Adithya ; et al. | 2022-09-15 |
Wide Voltage Range Level Shifter With Reduced Duty Cycle Distortion Across Operating Conditions
App 20220021389 - PONNA; Narender ; et al. | 2022-01-20 |
Wide voltage range level shifter with reduced duty cycle distortion across operating conditions
Grant 11,228,312 - Ponna , et al. January 18, 2 | 2022-01-18 |
Systems and methods for control signal latching in memories
Grant 11,152,921 - Boda , et al. October 19, 2 | 2021-10-19 |
Write assist circuitry for memory
Grant 11,049,552 - Raj , et al. June 29, 2 | 2021-06-29 |
Area efficient write data path circuit for SRAM yield enhancement
Grant 10,867,668 - Gupta , et al. December 15, 2 | 2020-12-15 |
Access assist with wordline adjustment with tracking cell
Grant 10,811,088 - Raj , et al. October 20, 2 | 2020-10-20 |
SRAM write yield enhancement with pull-up strength modulation
Grant 10,811,086 - Mohanty , et al. October 20, 2 | 2020-10-20 |
Access Assist With Wordline Adjustment With Tracking Cell
App 20200294580 - Raj; Pradeep ; et al. | 2020-09-17 |
Flexible power sequencing for dual-power memory
Grant 10,446,196 - Narasimhan , et al. Oc | 2019-10-15 |
Area Efficient Write Data Path Circuit For Sram Yield Enhancement
App 20190108872 - GUPTA; Sharad Kumar ; et al. | 2019-04-11 |
Noise immune data path scheme for multi-bank memory architecture
Grant 10,140,224 - Narasimhan , et al. Nov | 2018-11-27 |
Noise Immune Data Path Scheme For Multi-bank Memory Architecture
App 20180113821 - NARASIMHAN; Mukund ; et al. | 2018-04-26 |
Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
Grant 9,947,419 - Sinha , et al. April 17, 2 | 2018-04-17 |
Wordline adjustment scheme
Grant 9,928,898 - Sahu , et al. March 27, 2 | 2018-03-27 |
Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories
Grant 9,928,889 - Narasimhan , et al. March 27, 2 | 2018-03-27 |
Boost charge recycle for low-power memory
Grant 9,875,790 - Sinha , et al. January 23, 2 | 2018-01-23 |
Bit writability implementation for memories
Grant 9,875,776 - Mathuria , et al. January 23, 2 | 2018-01-23 |
Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
Grant 9,865,316 - Gupta , et al. January 9, 2 | 2018-01-09 |
Apparatus and method for controlling boost capacitance for low power memory circuits
Grant 9,837,144 - Sinha , et al. December 5, 2 | 2017-12-05 |
Wordline Adjustment Scheme
App 20170287551 - SAHU; Rahul ; et al. | 2017-10-05 |
Architecture to improve write-ability in SRAM
Grant 9,721,650 - Raj , et al. August 1, 2 | 2017-08-01 |
Memory With Improved Write Time And Reduced Write Power
App 20170213587 - Gupta; Sharad Kumar ; et al. | 2017-07-27 |
Pulse latch reset tracking at high differential voltage
Grant 9,607,674 - Narasimhan , et al. March 28, 2 | 2017-03-28 |
Segmented ternary content addressable memory search architecture
Grant 7,804,699 - Gupta , et al. September 28, 2 | 2010-09-28 |
Segmented Ternary Content Addressable Memory Search Architecture
App 20100165690 - Gupta; Sharad Kumar ; et al. | 2010-07-01 |
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