Gunaratna; Senani

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gunaratna; Senani.The latest application filed is for "multiple mode device implementation for programmable logic devices".

Company Profile

3.12.9

Gunaratna; Senani - Los Gatos CA
Gunaratna, Senani - Campbell CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multiple mode device implementation for programmable logic devices Grant 10,630,269 - Sharpe-Geisler , et al.	2020-04-21
Flexible ripple mode device implementation for programmable logic devices Grant 10,382,021 - Sharpe-Geisler , et al. A	2019-08-13
Multiple Mode Device Implementation For Programmable Logic Devices App 20190158073 - Sharpe-Geisler; Brad ; et al.	2019-05-23
Multiple mode device implementation for programmable logic devices Grant 10,141,917 - Sharpe-Geisler , et al. Nov	2018-11-27
Selective power gating of routing resource configuration memory bits for programmable logic devices Grant 10,079,054 - Gunaratna , et al. September 18, 2	2018-09-18
Flexible ripple mode device implementation for programmable logic devices Grant 9,735,761 - Sharpe-Geisler , et al. August 15, 2	2017-08-15
Multiple mode device implementation for programmable logic devices Grant 9,716,491 - Sharpe-Geisler , et al. July 25, 2	2017-07-25
High speed complementary NMOS LUT logic Grant 9,543,950 - Sharpe-Geisler , et al. January 10, 2	2017-01-10
Shared logic for multiple registers with asynchronous initialization Grant 9,252,755 - Sharpe-Geisler , et al. February 2, 2	2016-02-02
Multiple Mode Device Implementation For Programmable Logic Devices App 20160028401 - Sharpe-Geisler; Brad ; et al.	2016-01-28
Shared Logic For Multiple Registers With Asynchronous Initialization App 20160028383 - Sharpe-Geisler; Brad ; et al.	2016-01-28
Flexible Ripple Mode Device Implementation For Programmable Logic Devices App 20160028400 - Sharpe-Geisler; Brad ; et al.	2016-01-28
High Speed Complementary Nmos Lut Logic App 20160020767 - Sharpe-Geisler; Brad ; et al.	2016-01-21
Adjustable interface buffer circuit between a programmable logic device and a dedicated device Grant 8,487,652 - Yap , et al. July 16, 2	2013-07-16
Adjustable Interface Buffer Circuit Between A Programmable Logic Device And A Dedicated Device App 20110298492 - Yap; Ket-Chong ; et al.	2011-12-08
Adjustable interface buffer circuit between a programmable logic device and a dedicated device Grant 8,018,248 - Yap , et al. September 13, 2	2011-09-13
Low Power Programmable Logic Devices App 20110074464 - Gunaratna; Senani ; et al.	2011-03-31
Dynamic clock control Grant 7,443,222 - Saxe , et al. October 28, 2	2008-10-28
Adjustable interface buffer circuit between a programmable logic device and a dedicated device App 20080074141 - Yap; Ket-Chong ; et al.	2008-03-27
Serializer/deserializer Embedded In A Programmable Device App 20030039168 - Chan, Andrew K. ; et al.	2003-02-27

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