GULER; Leonard P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for GULER; Leonard P..The latest application filed is for "self-aligned gate endcap (sage) architectures with gate-all-around devices having epitaxial source or drain structures".

Company Profile

22.13.35

GULER; Leonard P. - Hillsboro OR
Guler; Leonard P - Hillsboro OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Having Epitaxial Source Or Drain Structures App 20220254893 - GULER; Leonard P. ; et al.	2022-08-11
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions Grant 11,398,474 - Guler , et al. July 26, 2	2022-07-26
Fin Shaping Using Templates And Integrated Circuit Structures Resulting Therefrom App 20220199792 - GULER; Leonard P. ; et al.	2022-06-23
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures Grant 11,355,608 - Guler , et al. June 7, 2	2022-06-07
Enhanced Grating Aligned Patterning For Euv Direct Print Processes App 20220172857 - M BARGHI; Seyedhamed ; et al.	2022-06-02
Vertical Metal Splitting Using Helmets And Wrap-around Dielectric Spacers App 20220157708 - Guler; Leonard P. ; et al.	2022-05-19
Fin shaping using templates and integrated circuit structures resulting therefrom Grant 11,302,790 - Guler , et al. April 12, 2	2022-04-12
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices App 20220102557 - GUHA; Biswajeet ; et al.	2022-03-31
Fabrication Of Gate-all-around Integrated Circuit Structures Having Adjacent Island Structures App 20220093589 - GULER; Leonard P. ; et al.	2022-03-24
Fabrication Of Gate-all-around Integrated Circuit Structures Having Pre-spacer Deposition Cut Gates App 20220093592 - GULER; Leonard P. ; et al.	2022-03-24
Selective Growth Self-aligned Gate Endcap (sage) Architectures Without Fin End Gap App 20220093590 - GULER; Leonard P. ; et al.	2022-03-24
Integrated Nanowire & Nanoribbon Patterning In Transistor Manufacture App 20220051946 - Guler; Leonard P. ; et al.	2022-02-17
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Grant 11,233,152 - Guha , et al. January 25, 2	2022-01-25
Gate isolation in non-planar transistors Grant 11,227,863 - Guler , et al. January 18, 2	2022-01-18
Plug And Recess Process For Dual Metal Gate On Stacked Nanoribbon Devices App 20210408257 - THOMAS; Nicole ; et al.	2021-12-30
Integrated nanowire and nanoribbon patterning in transistor manufacture Grant 11,164,790 - Guler , et al. November 2, 2	2021-11-02
Via & Plug Architectures For Integrated Circuit Interconnects & Methods Of Manufacture App 20210313222 - Guler; Leonard P. ; et al.	2021-10-07
Gate-all-around Integrated Circuit Structures Having Fin Stack Isolation App 20210305430 - GULER; Leonard P. ; et al.	2021-09-30
Self-aligned Gate Edge Trigate And Finfet Devices App 20210249411 - LIAO; Szuya S. ; et al.	2021-08-12
Directional spacer removal for integrated circuit structures Grant 11,056,397 - Guler , et al. July 6, 2	2021-07-06
Gate-all-around Integrated Circuit Structures Having Low Aspect Ratio Isolation Structures And Subfins App 20210202478 - GUHA; Biswajeet ; et al.	2021-07-01
Self-aligned gate edge trigate and finFET devices Grant 11,043,492 - Liao , et al. June 22, 2	2021-06-22
Contact Over Active Gate Structures With Metal Oxide Layers To Inhibit Shorting App 20210090990 - HOURANI; Rami ; et al.	2021-03-25
Depop Using Cyclic Selective Spacer Etch App 20200411661 - GULER; Leonard P. ; et al.	2020-12-31
Vertical Edge Blocking (veb) Technique For Increasing Patterning Process Margin App 20200388530 - GULER; Leonard P. ; et al.	2020-12-10
Fin Shaping Using Templates And Integrated Circuit Structures Resulting Therefrom App 20200388689 - GULER; Leonard P. ; et al.	2020-12-10
1d Vertical Edge Blocking (veb) Via And Plug App 20200388534 - GULER; Leonard P. ; et al.	2020-12-10
Gate Isolation In Non-planar Transistors App 20200373299 - Guler; Leonard P. ; et al.	2020-11-26
Directional Spacer Removal For Integrated Circuit Structures App 20200373205 - Guler; Leonard P. ; et al.	2020-11-26
Gate isolation in non-planar transistors Grant 10,797,047 - Guler , et al. October 6, 2	2020-10-06
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Above Insulator Substrates App 20200219990 - GUHA; Biswajeet ; et al.	2020-07-09
Gate-all-around Integrated Circuit Structures Having Oxide Sub-fins App 20200219978 - GULER; Leonard P. ; et al.	2020-07-09
Integrated Nanowire & Nanoribbon Patterning In Transistor Manufacture App 20200176321 - Guler; Leonard P/ ; et al.	2020-06-04
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Having Epitaxial Source Or Drain Structures App 20200098878 - GULER; Leonard P. ; et al.	2020-03-26
Neighboring Gate-all-around Integrated Circuit Structures Having Disjoined Epitaxial Source Or Drain Regions App 20200091144 - GULER; Leonard P. ; et al.	2020-03-19
Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom Grant 10,559,529 - Wallace , et al. Feb	2020-02-11
Self-aligned build-up of topographic features Grant 10,541,143 - Guler , et al. Ja	2020-01-21
Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom Grant 10,522,402 - Guler Dec	2019-12-31
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices App 20190393352 - GUHA; Biswajeet ; et al.	2019-12-26
Self-aligned Gate Edge Trigate And Finfet Devices App 20190139957 - LIAO; Szuya S. ; et al.	2019-05-09
Self-aligned Build-up Of Topographic Features App 20190096685 - Guler; Leonard P. ; et al.	2019-03-28
Pitch Division Patterning Approaches With Increased Overlay Margin For Back End Of Line (beol) Interconnect Fabrication And Structures Resulting Therefrom App 20190019748 - WALLACE; Charles H. ; et al.	2019-01-17
Gate Isolation In Non-planar Transistors App 20180331098 - Guler; Leonard P. ; et al.	2018-11-15
Grid Self-aligned Metal Via Processing Schemes For Back End Of Line (beol) Interconnects And Structures Resulting Therefrom App 20180308754 - GULER; Leonard P.	2018-10-25
Sacrificial material for stripping masking layers Grant 9,916,988 - Sundararajan , et al. March 13, 2	2018-03-13
Sacrificial Material For Stripping Masking Layers App 20160203999 - SUNDARARAJAN; SHAKUNTALA ; et al.	2016-07-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.