Gujral; Manoj

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gujral; Manoj.The latest application filed is for "multiprocessor system having an input/output (i/o) bridge circuit for transferring data between volatile and non-volatile memory".

Company Profile

0.7.2

Gujral; Manoj - Los Altos CA
Gujral; Manoj - Mission Viejo CA
Gujral; Manoj - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory Grant 8,060,708 - Maheshwari , et al. November 15, 2	2011-11-15
Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory App 20100312952 - Maheshwari; Dinesh ; et al.	2010-12-09
Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory Grant 7,730,268 - Maheshwari , et al. June 1, 2	2010-06-01
Multiprocessor System having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory App 20080046638 - Maheshwari; Dinesh ; et al.	2008-02-21
Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states Grant 6,223,260 - Gujral , et al. April 24, 2	2001-04-24
Multiprocessor with split transaction bus architecture providing cache tag and address compare for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag Grant 6,032,231 - Gujral February 29, 2	2000-02-29
Method for cycle request with quick termination without waiting for the cycle to reach the destination by storing information in queue Grant 5,822,611 - Donley , et al. October 13, 1	1998-10-13
Livelock avoidance Grant 5,761,446 - Donley , et al. June 2, 1	1998-06-02
Multiprocessor with split transaction bus architecture for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag Grant 5,732,244 - Gujral March 24, 1	1998-03-24

Company Registrations

SEC

0001490064

Gujral Manoj

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