Guillot; Jean-Michel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Guillot; Jean-Michel.The latest application filed is for "method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands".

Company Profile

0.8.6

Guillot; Jean-Michel - Paris FR
Guillot; Jean-Michel - Cloyne IE
Guillot; Jean-Michel - Clyone IL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Glass Grant D659,476 - Guillot May 15, 2	2012-05-15
Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands Grant 8,049,271 - Blanchard , et al. November 1, 2	2011-11-01
Method For Fabricating A Power Semiconductor Device Having A Voltage Sustaining Layer With A Terraced Trench Facilitating Formation Of Floating Islands App 20100207198 - Blanchard; Richard A. ; et al.	2010-08-19
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands Grant 7,736,976 - Blanchard , et al. June 15, 2	2010-06-15
Method For Fabricating A Power Semiconductor Device Having A Voltage Sustaining Layer With A Terraced Trench Facilitating Formation Of Floating Islands App 20080142880 - Blanchard; Richard A. ; et al.	2008-06-19
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands Grant 7,304,347 - Blanchard , et al. December 4, 2	2007-12-04
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands App 20040097028 - Blanchard, Richard A. ; et al.	2004-05-20
Transient voltage suppressor having an epitaxial layer for higher avalanche voltage operation App 20040075160 - Eng, Jack ; et al.	2004-04-22
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands Grant 6,649,477 - Blanchard , et al. November 18, 2	2003-11-18
Method for fabricating a power semiconductor device having a floating island voltage sustaining layer Grant 6,624,494 - Blanchard , et al. September 23, 2	2003-09-23
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating Islands App 20030068854 - Blanchard, Richard A. ; et al.	2003-04-10
Method for fabricating a power semiconductor device having a floating island voltage sustaining layer App 20030068863 - Blanchard, Richard A. ; et al.	2003-04-10
Method for fabricating a power semiconductor device having a floating island voltage sustaining layer Grant 6,465,304 - Blanchard , et al. October 15, 2	2002-10-15
Planar P-N junction semiconductor structure with multilayer passivation Grant 5,677,562 - Korwin-Pawlowski , et al. October 14, 1	1997-10-14

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