Guettaf; Amar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Guettaf; Amar.The latest application filed is for "integrated circuit allowing for testing and isolation of integrated power management unit".

Company Profile

0.17.20

Guettaf; Amar - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode Grant 8,856,559 - Alarcon , et al. October 7, 2	2014-10-07
Integrated Circuit Allowing For Testing And Isolation Of Integrated Power Management Unit App 20130047000 - ALARCON; Veronica ; et al.	2013-02-21
Control of tristate buses during scan test Grant 8,310,263 - Kodihalli , et al. November 13, 2	2012-11-13
Protecting data on integrated circuit Grant 8,074,132 - Guettaf , et al. December 6, 2	2011-12-06
Protecting Data On Integrated Circuit App 20100107023 - Guettaf; Amar ; et al.	2010-04-29
Methods and computer program products for debugging clock-related scan testing failures of integrated circuits Grant 7,581,150 - Guettaf August 25, 2	2009-08-25
Debug method for mismatches occurring during the simulation of scan patterns Grant 7,558,722 - Guettaf July 7, 2	2009-07-07
Systems and methods for controlling clock signals during scan testing integrated circuits Grant 7,500,165 - Guettaf March 3, 2	2009-03-03
Scan Clock Architecture Supporting Slow Speed Scan, At Speed Scan, And Logic Bist App 20080282110 - Guettaf; Amar	2008-11-13
Single Scan Clock In A Multi-clock Domain App 20080282122 - Guettaf; Amar	2008-11-13
Memory bypass with support for path delay test Grant 7,441,164 - Guettaf October 21, 2	2008-10-21
System and method for clock domain grouping using data path relationships Grant 7,424,417 - Guettaf September 9, 2	2008-09-09
Methods for debugging scan testing failures of integrated circuits Grant 7,395,468 - Guettaf July 1, 2	2008-07-01
JTAG boundary scan compliant testing architecture with full and partial disable App 20080082879 - Guettaf; Amar	2008-04-03
Systems and methods for scan test access using bond pad test access circuits Grant 7,131,045 - Guettaf October 31, 2	2006-10-31
Scan testing mode control of gated clock signals for flip-flops Grant 7,089,471 - Guettaf August 8, 2	2006-08-08
Methodology for selectively testing portions of an integrated circuit Grant 7,062,693 - Sweet , et al. June 13, 2	2006-06-13
Scan testing mode control of gated clock signals for memory devices Grant 7,058,868 - Guettaf June 6, 2	2006-06-06
System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains Grant 7,032,202 - Guettaf , et al. April 18, 2	2006-04-18
Systems and methods for controlling clock signals during scan testing integrated circuits App 20060075297 - Guettaf; Amar	2006-04-06
Methods and computer program products for debugging clock-related scan testing failures of integrated circuits App 20060069972 - Guettaf; Amar	2006-03-30
System and method for using IDDQ pattern generation for burn-in tests Grant 6,968,519 - Guettaf November 22, 2	2005-11-22
Methods for debugging scan testing failures of integrated circuits App 20050216805 - Guettaf, Amar	2005-09-29
Control of tristate buses during scan test App 20050060623 - Kodihalli, Himakiran ; et al.	2005-03-17
Scan testing mode control of gated clock signals for memory devices App 20050039095 - Guettaf, Amar	2005-02-17
Systems and methods for scan test access using bond pad test access circuits App 20050039097 - Guettaf, Amar	2005-02-17
Scan testing mode control of gated clock signals for flip-flops App 20050039096 - Guettaf, Amar	2005-02-17
Control of tristate buses during scan test Grant 6,822,439 - Kodihalli , et al. November 23, 2	2004-11-23
Methodology for selectively testing portions of an integrated circuit App 20040210807 - Sweet, James ; et al.	2004-10-21
Control of tristate buses during scan test App 20040153929 - Kodihalli, Himakiran ; et al.	2004-08-05
System and method for using IDDQ pattern generation for burn-in tests App 20040153932 - Guettaf, Amar	2004-08-05
Memory bypass with support for path delay test App 20040128604 - Guettaf, Amar	2004-07-01
System and method for clock domain grouping using data path relationships App 20040098241 - Guettaf, Amar	2004-05-20
Debug method for mismatches occurring during the simulation of scan patterns App 20040098239 - Guettaf, Amar	2004-05-20
System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains App 20040098687 - Guettaf, Amar ; et al.	2004-05-20

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