Guccione; Steven A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Guccione; Steven A..The latest application filed is for "allocating field-programmable gate array (fpga) resources".

Company Profile

0.21.3

Guccione; Steven A. - Austin TX
Guccione; Steven A. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Allocating field-programmable gate array (FPGA) resources Grant 9,940,166 - Guccione April 10, 2	2018-04-10
Allocating field-programmable gate array (FPGA) resources Grant 9,600,356 - Guccione March 21, 2	2017-03-21
Allocating Field-programmable Gate Array (fpga) Resources App 20170017523 - Guccione; Steven A.	2017-01-19
Allocating Field-programmable Gate Array (fpga) Resources App 20170017539 - Guccione; Steven A.	2017-01-19
Pipelined multiply-scan circuit Grant 9,459,832 - Guccione October 4, 2	2016-10-04
Pipelined Multiply-scan Circuit App 20150363168 - Guccione; Steven A.	2015-12-17
Method and system for device-level simulation of a circuit design for a programmable logic device Grant 6,922,665 - Guccione , et al. July 26, 2	2005-07-26
Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD Grant 6,836,842 - Guccione , et al. December 28, 2	2004-12-28
Run-time reconfigurable testing of programmable logic devices Grant 6,668,237 - Guccione , et al. December 23, 2	2003-12-23
Adaptable configuration interface for a programmable logic device Grant 6,665,766 - Guccione , et al. December 16, 2	2003-12-16
Method of configuring FPGAS for dynamically reconfigurable computing Grant 6,557,156 - Guccione April 29, 2	2003-04-29
Method and apparatus for relocating elements in an evolvable configuration bitstream Grant 6,539,532 - Levi , et al. March 25, 2	2003-03-25
Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores Grant 6,530,071 - Guccione , et al. March 4, 2	2003-03-04
Run-time routing for programmable logic devices Grant 6,487,709 - Keller , et al. November 26, 2	2002-11-26
Method and apparatus for evolving configuration bitstreams Grant 6,430,736 - Levi , et al. August 6, 2	2002-08-06
Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel Grant 6,378,122 - Levi , et al. April 23, 2	2002-04-23
Method and apparatus for remotely evolving configuration bitstreams Grant 6,363,517 - Levi , et al. March 26, 2	2002-03-26
Method and apparatus for testing evolvable configuration bitstreams Grant 6,363,519 - Levi , et al. March 26, 2	2002-03-26
Content-addressable memory implemented using programmable logic Grant 6,351,143 - Guccione , et al. February 26, 2	2002-02-26
Content-addressable memory implemented using programmable logic Grant 6,278,289 - Guccione , et al. August 21, 2	2001-08-21
Configuration of programmable logic devices with routing core generators Grant 6,216,259 - Guccione , et al. April 10, 2	2001-04-10
Method of designing FPGAs for dynamically reconfigurable computing Grant 6,078,736 - Guccione June 20, 2	2000-06-20
Method for generating a software class compatible with two or more interpreters Grant 6,074,432 - Guccione June 13, 2	2000-06-13
Network configuration of programmable circuits Grant 5,995,744 - Guccione November 30, 1	1999-11-30

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