| Patent | Date |
|---|
Self-aligned planar double-gate transistor structure
Grant 7,960,790 - Dokumaci , et al. June 14, 2 | 2011-06-14 |
Integration of strained Ge into advanced CMOS technology
Grant 7,790,538 - Shang , et al. September 7, 2 | 2010-09-07 |
Three dimensional integrated circuit and method of design
Grant 7,723,207 - Alam , et al. May 25, 2 | 2010-05-25 |
High-performance CMOS SOI devices on hybrid crystal-oriented substrates
Grant 7,713,807 - Doris , et al. May 11, 2 | 2010-05-11 |
Self-aligned planar double-gate transistor structure
Grant 7,453,123 - Dokumaci , et al. November 18, 2 | 2008-11-18 |
Integration of strained Ge into advanced CMOS technology
App 20080248616 - Shang; Huiling ; et al. | 2008-10-09 |
Self-aligned Planar Double-gate Transistor Structure
App 20080246090 - Dokumaci; Omer H. ; et al. | 2008-10-09 |
Three-dimensional Architecture For Self-checking And Self-repairing Integrated Circuits
App 20080165521 - BERNSTEIN; KERRY ; et al. | 2008-07-10 |
Integration of strained Ge into advanced CMOS technology
Grant 7,387,925 - Shang , et al. June 17, 2 | 2008-06-17 |
High-performance Cmos Soi Devices On Hybrid Crystal-oriented Substrates
App 20080096330 - Doris; Bruce B. ; et al. | 2008-04-24 |
Connection device with actuating element for changing a conductive state of a via
Grant 7,342,301 - Frank , et al. March 11, 2 | 2008-03-11 |
Three Dimensional Integrated Circuit And Method Of Design
App 20080042140 - Alam; Syed M. ; et al. | 2008-02-21 |
High-performance CMOS devices on hybrid crystal oriented substrates
Grant 7,329,923 - Doris , et al. February 12, 2 | 2008-02-12 |
Three dimensional integrated circuit
Grant 7,312,487 - Alam , et al. December 25, 2 | 2007-12-25 |
Three Dimensional Integrated Circuit And Method Of Design
App 20070287224 - Alam; Syed M. ; et al. | 2007-12-13 |
Integration of strained Ge into advanced CMOS technology
App 20070218621 - Shang; Huiling ; et al. | 2007-09-20 |
Integration of strained Ge into advanced CMOS technology
Grant 7,244,958 - Shang , et al. July 17, 2 | 2007-07-17 |
Self-aligned Planar Double-gate Process By Self-aligned Oxidation
App 20070138556 - Dokumaci; Omer H. ; et al. | 2007-06-21 |
Self-aligned planar double-gate process by self-aligned oxidation
Grant 7,205,185 - Dokumaci , et al. April 17, 2 | 2007-04-17 |
Compressive SiGe <110> growth and structure of MOSFET devices
Grant 7,187,059 - Chan , et al. March 6, 2 | 2007-03-06 |
Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes
Grant 7,138,683 - Guarini , et al. November 21, 2 | 2006-11-21 |
Connection device
App 20060214301 - Frank; David J. ; et al. | 2006-09-28 |
Method of fabricating a connection device
Grant 7,074,707 - Frank , et al. July 11, 2 | 2006-07-11 |
Three dimensional integrated circuit and method of design
App 20060033110 - Alam; Syed M. ; et al. | 2006-02-16 |
Compressive SiGe <110> growth and structure of MOSFET devices
App 20050285159 - Chan, Kevin K. ; et al. | 2005-12-29 |
Integration of strained Ge into advanced CMOS technology
App 20050285097 - Shang, Huiling ; et al. | 2005-12-29 |
Strained silicon CMOS on hybrid crystal orientations
App 20050236687 - Chan, Kevin K. ; et al. | 2005-10-27 |
Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
Grant 6,911,375 - Guarini , et al. June 28, 2 | 2005-06-28 |
Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes
App 20050070077 - Guarini, Kathryn W. ; et al. | 2005-03-31 |
Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
App 20050067620 - Chan, Victor ; et al. | 2005-03-31 |
Self-aligned planar double-gate process by self-aligned oxidation
App 20050059252 - Dokumaci, Omer H. ; et al. | 2005-03-17 |
Connection device and method of forming a connection device
App 20050056937 - Frank, David J. ; et al. | 2005-03-17 |
High-performance CMOS devices on hybrid crystal oriented substrates
App 20040256700 - Doris, Bruce B. ; et al. | 2004-12-23 |
Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
Grant 6,830,962 - Guarini , et al. December 14, 2 | 2004-12-14 |
Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
App 20040241958 - Guarini, Kathryn W. ; et al. | 2004-12-02 |
Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
Grant 6,821,826 - Chan , et al. November 23, 2 | 2004-11-23 |
Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby
Grant 6,803,266 - Solomon , et al. October 12, 2 | 2004-10-12 |
Thin film nanostructures
App 20040142578 - Wiesner, Ulrich ; et al. | 2004-07-22 |
Inorganic nanoporous membranes and methods to form same
App 20040124092 - Black, Charles T. ; et al. | 2004-07-01 |
MOS device having a passivated semiconductor-dielectric interface
Grant 6,603,181 - Solomon , et al. August 5, 2 | 2003-08-05 |
Process For Passivating The Semiconductor-dielectric Interface Of A Mos Device And Mos Device Formed Thereby
App 20030132492 - Solomon , Paul M. ; et al. | 2003-07-17 |
Semiconductor with nanoscale features
Grant 6,506,660 - Holmes , et al. January 14, 2 | 2003-01-14 |
Mos Device Having A Passivated Semiconductor-dielectric Interface
App 20020094643 - Solomon, Paul M. ; et al. | 2002-07-18 |
Semiconductor capacitors
App 20020058394 - Holmes, Steven J. ; et al. | 2002-05-16 |
Method for increasing the capacitance of a semiconductor capacitors
Grant 6,358,813 - Holmes , et al. March 19, 2 | 2002-03-19 |
| 