Gruening; Ulrike

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gruening; Ulrike.The latest application filed is for "semiconductor structures and manufacturing methods".

Company Profile

0.28.8

Gruening; Ulrike - Munchen DE
Gruening; Ulrike - Munich DE
Gruening, Ulrike - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for fabricating a semiconductor structure Grant 6,967,133 - Amon , et al. November 22, 2	2005-11-22
Trench capacitor memory cell Grant 6,812,091 - Gruening , et al. November 2, 2	2004-11-02
Semiconductor structures and manufacturing methods App 20040209474 - Tews, Helmut Horst ; et al.	2004-10-21
Field-shield-trench isolation for gigabit DRAMs Grant 6,762,447 - Mandelman , et al. July 13, 2	2004-07-13
Self-aligned near surface strap for high density trench DRAMS Grant 6,759,291 - Divakaruni , et al. July 6, 2	2004-07-06
Method for fabricating a semiconductor structure App 20040115874 - Amon, Jurgen ; et al.	2004-06-17
Semiconductor structures and manufacturing methods Grant 6,740,555 - Tews , et al. May 25, 2	2004-05-25
Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect Grant 6,727,539 - Divakaruni , et al. April 27, 2	2004-04-27
Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch Grant 6,630,379 - Mandelman , et al. October 7, 2	2003-10-07
Semiconductor structures and manufacturing methods Grant 6,605,860 - Tews , et al. August 12, 2	2003-08-12
Structure and method for forming a body contact for vertical transistor cells Grant 6,593,612 - Gruening , et al. July 15, 2	2003-07-15
Self-aligned buried strap for vertical transistors Grant 6,555,862 - Mandelman , et al. April 29, 2	2003-04-29
Dynamic random access memory Grant 6,544,850 - Schnabel , et al. April 8, 2	2003-04-08
Embedded vertical dram arrays with silicided bitline and polysilicon interconnect App 20030003651 - Divakaruni, Ramachandra ; et al.	2003-01-02
Integrated circuit trench device with a dielectric collar stack, and method of forming thereof Grant 6,486,024 - Tews , et al. November 26, 2	2002-11-26
Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect Grant 6,429,068 - Divakaruni , et al. August 6, 2	2002-08-06
Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch App 20020085434 - Mandelman, Jack A. ; et al.	2002-07-04
Self-aligned near surface strap for high density trench drams App 20020079528 - Divakaruni, Ramachandra ; et al.	2002-06-27
Structure and method for forming a body contact for vertical transistor cells App 20020066925 - Gruening, Ulrike ; et al.	2002-06-06
Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates Grant 6,362,040 - Tews , et al. March 26, 2	2002-03-26
Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure Grant 6,348,374 - Athavale , et al. February 19, 2	2002-02-19
Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch Grant 6,339,241 - Mandelman , et al. January 15, 2	2002-01-15
Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region App 20020004290 - Gruening, Ulrike ; et al.	2002-01-10
Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAM Grant 6,331,459 - Gruening December 18, 2	2001-12-18
Method for fabricating transistors Grant 6,323,103 - Rengarajan , et al. November 27, 2	2001-11-27
Semiconductor structure and manufacturing methods Grant 6,319,788 - Gruening , et al. November 20, 2	2001-11-20
Process for manufacturing a crystal axis-aligned vertical side wall device App 20010038113 - Bronner, Gary ; et al.	2001-11-08
Memory cell structure and fabrication Grant 6,265,742 - Gruening , et al. July 24, 2	2001-07-24
Embedded vertical DRAM cells and dual workfunction logic gates Grant 6,258,659 - Gruening , et al. July 10, 2	2001-07-10
Dynamic random access memory Grant 6,255,683 - Radens , et al. July 3, 2	2001-07-03
Quantum conductive recrystallization barrier layers Grant 6,194,736 - Chaloux , et al. February 27, 2	2001-02-27
Low-resistance salicide fill for trench capacitors Grant 6,194,755 - Gambino , et al. February 27, 2	2001-02-27
Formation of controlled trench top isolation layers for vertical transistors Grant 6,177,698 - Gruening , et al. January 23, 2	2001-01-23
Vertical DRAM cell with wordline self-aligned to storage trench Grant 6,153,902 - Furukawa , et al. November 28, 2	2000-11-28
Memory cell structure and fabrication Grant 6,093,614 - Gruening , et al. July 25, 2	2000-07-25
Buffer layer for improving control of layer thickness Grant 6,013,937 - Beintner , et al. January 11, 2	2000-01-11

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