Grudowski; Paul A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Grudowski; Paul A..The latest application filed is for "gate security feature".

Company Profile

0.29.34

Grudowski; Paul A. - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device including an active region and two layers having different stress characteristics Grant 9,847,389 - Winstead , et al. December 19, 2	2017-12-19
Gate security feature Grant 8,980,734 - Stephens , et al. March 17, 2	2015-03-17
Gate Security Feature App 20140252487 - Stephens; Tab A. ; et al.	2014-09-11
Semiconductor Device Including An Active Region And Two Layers Having Different Stress Characteristics App 20140054704 - Winstead; Brian A. ; et al.	2014-02-27
Semiconductor device including an active region and two layers having different stress characteristics Grant 8,569,858 - Winstead , et al. October 29, 2	2013-10-29
Process of forming an electronic device including insulating layers having different strains Grant 8,021,957 - Grudowski , et al. September 20, 2	2011-09-20
Multilayer Silicon Nitride Deposition For A Semiconductor Device App 20110210401 - Junker; Kurt H. ; et al.	2011-09-01
Electronic device including insulating layers having different strains Grant 7,843,011 - Grudowski , et al. November 30, 2	2010-11-30
Method of forming a via Grant 7,745,298 - Stephens , et al. June 29, 2	2010-06-29
Method of making a semiconductor device with embedded stressor Grant 7,736,957 - Grudowski , et al. June 15, 2	2010-06-15
Electronic device including a transistor structure having an active region adjacent to a stressor layer Grant 7,714,318 - Adams , et al. May 11, 2	2010-05-11
Multilayer silicon nitride deposition for a semiconductor device Grant 7,700,499 - Junker , et al. April 20, 2	2010-04-20
Fabrication of a semiconductor device with stressor Grant 7,687,354 - Grudowski , et al. March 30, 2	2010-03-30
Method of forming a semiconductor device with multiple tensile stressor layers Grant 7,678,698 - Bo , et al. March 16, 2	2010-03-16
Fabrication Of A Semiconductor Device With Stressor App 20090221119 - Grudowski; Paul A. ; et al.	2009-09-03
Disposable organic spacers Grant 7,579,228 - Grudowski , et al. August 25, 2	2009-08-25
Method Of Forming A Via App 20090142895 - Stephens; Tab A. ; et al.	2009-06-04
Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors Grant 7,538,002 - Zhang , et al. May 26, 2	2009-05-26
Stressor integration and method thereof Grant 7,528,029 - Grudowski , et al. May 5, 2	2009-05-05
Semiconductor device having stressors and method for forming Grant 7,511,360 - Shroff , et al. March 31, 2	2009-03-31
Process for forming an electronic device including transistor structures with sidewall spacers Grant 7,504,289 - Lim , et al. March 17, 2	2009-03-17
Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility Grant 7,491,630 - Shroff , et al. February 17, 2	2009-02-17
Disposable organic spacers App 20090017587 - Grudowski; Paul A. ; et al.	2009-01-15
Electronic Device Including A Transistor Structure Having An Active Region Adjacent To A Stressor Layer App 20080296633 - Adams; Vance H. ; et al.	2008-12-04
Method Of Making A Semiconductor Device With Embedded Stressor App 20080299724 - Grudowski; Paul A. ; et al.	2008-12-04
Semiconductor Device With Stressors And Methods Thereof App 20080293192 - Zollner; Stefan ; et al.	2008-11-27
Semiconductor Device With Multiple Tensile Stressor Layers And Method App 20080272411 - Bo; Xiangzheng ; et al.	2008-11-06
Method of forming an interlayer dielectric Grant 7,442,598 - Grudowski , et al. October 28, 2	2008-10-28
Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device Grant 7,420,202 - Adams , et al. September 2, 2	2008-09-02
Anneal of epitaxial layer in a semiconductor device Grant 7,416,605 - Zollner , et al. August 26, 2	2008-08-26
Electronic Device Including Insulating Layers Having Different Strains And A Process For Forming The Electronic Device App 20080179679 - Grudowski; Paul A. ; et al.	2008-07-31
Multilayer silicon nitride deposition for a semiconductor device App 20080173986 - Junker; Kurt H. ; et al.	2008-07-24
Multilayer silicon nitride deposition for a semiconductor device App 20080173908 - Junker; Kurt H. ; et al.	2008-07-24
Method of making a nitrided gate dielectric Grant 7,402,472 - Lim , et al. July 22, 2	2008-07-22
Anneal Of Epitaxial Layer In A Semiconductor Device App 20080163813 - Zollner; Stefan ; et al.	2008-07-10
Integrated Circuit Having Tensile And Compressive Regions App 20080150072 - Winstead; Brian A. ; et al.	2008-06-26
Method For Forming A Stressor Layer App 20080026517 - Grudowski; Paul A. ; et al.	2008-01-31
Stressor integration and method thereof App 20070249113 - Grudowski; Paul A. ; et al.	2007-10-25
Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility App 20070218661 - Shroff; Mehul D. ; et al.	2007-09-20
Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors App 20070202651 - Zhang; Da ; et al.	2007-08-30
Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration App 20070197011 - Srivastava; Anadi ; et al.	2007-08-23
Semiconductor device having stressors and method for forming App 20070132031 - Shroff; Mehul D. ; et al.	2007-06-14
Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device App 20070102755 - Adams; Vance H. ; et al.	2007-05-10
Method of forming an electronic device Grant 7,214,590 - Lim , et al. May 8, 2	2007-05-08
Electronic device including transistor structures with sidewall spacers and a process for forming the electronic device App 20070090455 - Lim; Sangwoo ; et al.	2007-04-26
Method of forming an interlayer dielectric App 20060281240 - Grudowski; Paul A. ; et al.	2006-12-14
Transistor sidewall spacer stress modulation Grant 7,132,704 - Grudowski November 7, 2	2006-11-07
Method of forming an electronic device App 20060223266 - Lim; Sangwoo ; et al.	2006-10-05
Method of making a nitrided gate dielectric App 20060194423 - Lim; Sangwoo ; et al.	2006-08-31
Differentially nitrided gate dielectrics in CMOS fabrication process App 20060084220 - Lim; Sangwoo ; et al.	2006-04-20
Transistor sidewall spacer stress modulation App 20050156237 - Grudowski, Paul A.	2005-07-21
Integrated circuit device and method therefor App 20050156229 - Yeap, Geoffrey C-F ; et al.	2005-07-21
Transistor sidewall spacer stress modulation Grant 6,902,971 - Grudowski June 7, 2	2005-06-07
Semiconductor fabrication process using transistor spacers of differing widths Grant 6,864,135 - Grudowski , et al. March 8, 2	2005-03-08
Transistor Sidewall Spacer Stress Modulation App 20050020022 - Grudowski, Paul A.	2005-01-27
Integrated circuit device and method therefor Grant 6,846,716 - Yeap , et al. January 25, 2	2005-01-25
Integrated circuit device and method therefor App 20040124450 - Yeap, Geoffrey C-F ; et al.	2004-07-01
Semiconductor fabrication process using transistor spacers of differing widths App 20040087090 - Grudowski, Paul A. ; et al.	2004-05-06
Integrated Circuit Device And Method Therefor App 20030181028 - Yeap, Geoffrey C-F ; et al.	2003-09-25
Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same Grant 6,369,430 - Adetutu , et al. April 9, 2	2002-04-09

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