Grondalski; Robert S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Grondalski; Robert S..The latest application filed is for "method and system for the architecture and implementation of a conscious machine".

Company Profile

0.11.2

Grondalski; Robert S. - Austin TX
Grondalski; Robert S. - Maynard MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for the architecture and implementation of a conscious machine Grant 7,370,042 - Grondalski May 6, 2	2008-05-06
Method and system for the architecture and implementation of a conscious machine App 20040267802 - Grondalski, Robert S.	2004-12-30
Generation of sign extended shifted numerical values Grant 6,654,774 - Dhablania , et al. November 25, 2	2003-11-25
Method and apparatus for reduction of noise sensitivity in dynamic logic circuits Grant 6,603,333 - Vinh , et al. August 5, 2	2003-08-05
Method and apparatus for reduction of noise sensitivity in dynamic logic circuits App 20020067188 - Vinh, James ; et al.	2002-06-06
Simultaneous parity generating/reading circuit for massively parallel processing systems Grant 6,108,763 - Grondalski August 22, 2	2000-08-22
Shift register divided into a number of cells and a number of stages within each cell to permit bit and multiple bit shifting Grant 5,481,749 - Grondalski January 2, 1	1996-01-02
Mechanism for broadcasting data in a massively parallell array processing system Grant 5,305,462 - Grondalski April 19, 1	1994-04-19
Massively parallel array processing system Grant 5,276,895 - Grondalski January 4, 1	1994-01-04
Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register Grant 5,230,079 - Grondalski July 20, 1	1993-07-20
Massively parallel array processing system Grant 5,170,484 - Grondalski December 8, 1	1992-12-08
Systems for interconnecting and configuring plurality of memory elements by control of mode signals Grant 5,146,606 - Grondalski September 8, 1	1992-09-08
SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors Grant 4,985,832 - Grondalski January 15, 1	1991-01-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.