Grillberger; Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Grillberger; Michael.The latest application filed is for "methods of forming 3-d integrated semiconductor devices having intermediate heat spreading capabilities".

Company Profile

2.22.17

Grillberger; Michael - Radebeul DE
- Radebeul DE
Grillberger; Michael - R{dot over a

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities Grant 10,014,279 - Werner , et al. July 3, 2	2018-07-03
Methods Of Forming 3-d Integrated Semiconductor Devices Having Intermediate Heat Spreading Capabilities App 20160190104 - Werner; Thomas ; et al.	2016-06-30
3-D integrated semiconductor device comprising intermediate heat spreading capabilities Grant 9,318,468 - Werner , et al. April 19, 2	2016-04-19
Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems Grant 08920027 -	2014-12-30
Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems Grant 8,920,027 - Grillberger , et al. December 30, 2	2014-12-30
Semiconductor device comprising through hole vias having a stress relaxation mechanism Grant 8,598,714 - Huisinga , et al. December 3, 2	2013-12-03
Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime Grant 8,501,545 - Grillberger , et al. August 6, 2	2013-08-06
Stress reduction in chip packaging by a stress compensation region formed around the chip Grant 8,497,583 - Chumakov , et al. July 30, 2	2013-07-30
Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contacts Grant 8,479,578 - Geisler , et al. July 9, 2	2013-07-09
Stress reduction in chip packaging by using a low-temperature chip-package connection regime Grant 8,482,123 - Grillberger , et al. July 9, 2	2013-07-09
Reducing Patterning Variability Of Trenches In Metallization Layer Stacks With A Low-k Material By Reducing Contamination Of Trench Dielectrics App 20130130498 - Feustel; Frank ; et al.	2013-05-23
Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features Grant 8,399,335 - Huisinga , et al. March 19, 2	2013-03-19
Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics Grant 8,357,610 - Feustel , et al. January 22, 2	2013-01-22
3-D Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilites App 20120061818 - Werner; Thomas ; et al.	2012-03-15
Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime App 20120049350 - Grillberger; Michael ; et al.	2012-03-01
Applying Thermal Mechanical Characteristics of Complex Semiconductor Devices by Integrated Heating Systems App 20120051392 - Grillberger; Michael ; et al.	2012-03-01
Sophisticated Metallization Systems in Semiconductors Formed by Removing Damaged Dielectric Surface Layers After Forming the Metal Features App 20120001343 - Huisinga; Torsten ; et al.	2012-01-05
Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism App 20120001330 - Huisinga; Torsten ; et al.	2012-01-05
3-D integrated semiconductor device comprising intermediate heat spreading capabilities Grant 8,080,866 - Werner , et al. December 20, 2	2011-12-20
Stress Reduction in Chip Packaging by a Stress Compensation Region Formed Around the Chip App 20110291299 - Chumakov; Dmytro ; et al.	2011-12-01
Reduction of Mechanical Stress in Metal Stacks of Sophisticated Semiconductor Devices During Die-Substrate Soldering by an Enhanced Cool Down Regime App 20110244632 - Grillberger; Michael ; et al.	2011-10-06
Assessing Metal Stack Integrity In Sophisticated Semiconductor Devices By Mechanically Stressing Die Contacts App 20110209548 - Geisler; Holm ; et al.	2011-09-01
Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability Grant 7,982,313 - Grillberger , et al. July 19, 2	2011-07-19
Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices Grant 7,829,357 - Grillberger , et al. November 9, 2	2010-11-09
Semiconductor Device Comprising A Chip Internal Electrical Test Structure Allowing Electrical Measurements During The Fabrication Process App 20100252828 - Grillberger; Michael ; et al.	2010-10-07
Semiconductor Device Comprising A Distributed Interconnected Sensor Structure For Die Internal Monitoring Purposes App 20100109005 - Grillberger; Michael ; et al.	2010-05-06
3-d Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilities App 20100052134 - Werner; Thomas ; et al.	2010-03-04
Semiconductor Device Including Stress Relaxation Gaps For Enhancing Chip Package Interaction Stability App 20100052147 - Grillberger; Michael ; et al.	2010-03-04
Semiconductor Device Comprising Metal Lines With A Selectively Formed Dielectric Cap Layer App 20090294921 - Grillberger; Michael ; et al.	2009-12-03
Reducing Patterning Variability Of Trenches In Metallization Layer Stacks With A Low-k Material By Reducing Contamination Of Trench Dielectrics App 20090243116 - Feustel; Frank ; et al.	2009-10-01
Method And Test Structure For Monitoring Cmp Processes In Metallization Layers Of Semiconductor Devices App 20090140246 - Grillberger; Michael ; et al.	2009-06-04

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