loadpatents
name:-0.029389142990112
name:-0.023417949676514
name:-0.014050006866455
Gribok; Sergey Patent Filings

Gribok; Sergey

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gribok; Sergey.The latest application filed is for "machine learning training architecture for programmable devices".

Company Profile
14.27.29
  • Gribok; Sergey - Santa Clara CA
  • Gribok; Sergey - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Machine Learning Training Architecture For Programmable Devices
App 20220107783 - Langhammer; Martin ;   et al.
2022-04-07
Machine learning training architecture for programmable devices
Grant 11,210,063 - Langhammer , et al. December 28, 2
2021-12-28
Method and apparatus for performing synthesis for field programmable gate array embedded feature placement
Grant 11,080,019 - Langhammer , et al. August 3, 2
2021-08-03
Methods for using a multiplier to support multiple sub-multiplication operations
Grant 10,871,946 - Langhammer , et al. December 22, 2
2020-12-22
Method and apparatus for implementing an application aware system on a programmable logic device
Grant 10,867,090 - Baeckler , et al. December 15, 2
2020-12-15
Logic circuits with simultaneous dual function capability
Grant 10,790,829 - Langhammer , et al. September 29, 2
2020-09-29
Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension
Grant 10,732,932 - Pasca , et al.
2020-08-04
Logic circuits with augmented arithmetic densities
Grant 10,715,144 - Gribok , et al.
2020-07-14
Methods For Using A Multiplier Circuit To Support Multiple Sub-multiplications Using Bit Correction And Extension
App 20200142671 - Pasca; Bogdan ;   et al.
2020-05-07
Logic Circuits With Simultaneous Dual Function Capability
App 20200106442 - Langhammer; Martin ;   et al.
2020-04-02
Machine Learning Training Architecture For Programmable Devices
App 20200026494 - Langhammer; Martin ;   et al.
2020-01-23
Logic Circuits With Augmented Arithmetic Densities
App 20190288688 - Gribok; Sergey ;   et al.
2019-09-19
Method And Apparatus For Implementing An Application Aware System On A Programmable Logic Device
App 20190213289 - BAECKLER; Gregg William ;   et al.
2019-07-11
Method And Apparatus For Performing Multiplier Regularization
App 20190121927 - LANGHAMMER; Martin ;   et al.
2019-04-25
Method and apparatus for improving system operation by replacing components for performing division during design compilation
Grant 10,223,488 - Gribok
2019-03-05
Methods For Using A Multiplier To Support Multiple Sub-multiplication Operations
App 20190042198 - Langhammer; Martin ;   et al.
2019-02-07
Method And Apparatus For Performing Synthesis For Field Programmable Gate Array Embedded Feature Placement
App 20190042683 - LANGHAMMER; Martin ;   et al.
2019-02-07
RAM-based shift register with embedded addressing
Grant 10,102,892 - Gribok October 16, 2
2018-10-16
Method and Apparatus for Improving System Operation by Replacing Components for Performing Division During Design Compilation
App 20180025100 - Gribok; Sergey
2018-01-25
Variable node processing unit
Grant 9,239,704 - Andreev , et al. January 19, 2
2016-01-19
Via-configurable high-performance logic block involving transistor chains
Grant 8,957,398 - Andreev , et al. February 17, 2
2015-02-17
Via-configurable high-performance logic block architecture
Grant 8,735,857 - Andreev , et al. May 27, 2
2014-05-27
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
App 20140103985 - Andreev; Alexander ;   et al.
2014-04-17
Via-Configurable High-Performance Logic Block Involving Transistor Chains
App 20140028348 - Andreev; Alexander ;   et al.
2014-01-30
Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node
Grant 8,629,548 - Andreev , et al. January 14, 2
2014-01-14
Variable Node Processing Unit
App 20130254252 - Andreev; Alexander ;   et al.
2013-09-26
Variable node processing unit
Grant 8,443,033 - Andreev , et al. May 14, 2
2013-05-14
MEMS-based switching
Grant 8,436,700 - Schmit , et al. May 7, 2
2013-05-07
Cryptographic Random Number Generator Using Finite Field Operations
App 20120278372 - Gribok; Sergey ;   et al.
2012-11-01
Cryptographic random number generator using finite field operations
Grant 8,250,129 - Gribok , et al. August 21, 2
2012-08-21
Via-Configurable High-Performance Logic Block Architecture
App 20120161093 - Andreev; Alexander ;   et al.
2012-06-28
Methods and apparatus for programmable decoding of a plurality of code types
Grant 8,035,537 - Andreev , et al. October 11, 2
2011-10-11
Parallel LDPC Decoder
App 20110173510 - Andreev; Alexander ;   et al.
2011-07-14
Low Complexity LDPC Encoding Algorithm
App 20110099454 - Gribok; Sergey ;   et al.
2011-04-28
Parallel LDPC decoder
Grant 7,934,139 - Andreev , et al. April 26, 2
2011-04-26
Mems-based Switching
App 20110067982 - Schmit; Herman ;   et al.
2011-03-24
Low complexity LDPC encoding algorithm
Grant 7,913,149 - Gribok , et al. March 22, 2
2011-03-22
Variable Node Processing Unit
App 20100030835 - Andreev; Alexander ;   et al.
2010-02-04
Systems and methods for pipelined analog to digital conversion
Grant 7,656,340 - Gribok , et al. February 2, 2
2010-02-02
Methods And Apparatus For Programmable Decoding Of A Plurality Of Code Types
App 20090309770 - Andreev; Alexander ;   et al.
2009-12-17
Systems And Methods For Pipelined Analog To Digital Conversion
App 20090303093 - Gribok; Sergey ;   et al.
2009-12-10
Computational Architecture for Soft Decoding
App 20090287980 - Gribok; Sergey ;   et al.
2009-11-19
Built in self test transport controller architecture
Grant 7,546,505 - Gribok , et al. June 9, 2
2009-06-09
RRAM memory error emulation
Grant 7,493,519 - Andreev , et al. February 17, 2
2009-02-17
Cryptographic random number generator using finite field operations
App 20080320066 - Gribok; Sergey ;   et al.
2008-12-25
Low Complexity LDPC Encoding Algorithm
App 20080168334 - Gribok; Sergey ;   et al.
2008-07-10
Parallel LDPC Decoder
App 20080134008 - Andreev; Alexander ;   et al.
2008-06-05
Built in self test transport controller architecture
App 20080109688 - Gribok; Sergey ;   et al.
2008-05-08
Master controller architecture
Grant 7,308,633 - Andreev , et al. December 11, 2
2007-12-11
RRAM communication system
Grant 7,283,385 - Andreev , et al. October 16, 2
2007-10-16
RRAM memory error emulation
App 20070094534 - Andreev; Alexander E. ;   et al.
2007-04-26
RRAM communication system
App 20060136775 - Andreev; Alexander E. ;   et al.
2006-06-22
Master controller architecture
App 20060129874 - Andreev; Alexandre ;   et al.
2006-06-15

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