Gregor; Steven L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gregor; Steven L..The latest application filed is for "testing state retention logic in low power systems".

Company Profile

0.14.5

Gregor; Steven L. - Owego NY
Gregor; Steven L. - Endicott NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fault modeling for state retention logic Grant 8,296,703 - Chakravadhanula , et al. October 23, 2	2012-10-23
Testing state retention logic in low power systems Grant 8,271,226 - Chakravadhanula , et al. September 18, 2	2012-09-18
Testing State Retention Logic In Low Power Systems App 20090326854 - CHAKRAVADHANULA; Krishna ; et al.	2009-12-31
Programable multi-port memory BIST with compact microcode Grant 7,168,005 - Adams , et al. January 23, 2	2007-01-23
Method and apparatus for testing multi-port memories Grant 7,032,144 - Adams , et al. April 18, 2	2006-04-18
Two-dimensional redundancy calculation Grant 7,003,704 - Adams , et al. February 21, 2	2006-02-21
Built-in self test system and method for two-dimensional memory redundancy allocation Grant 6,907,554 - Adams , et al. June 14, 2	2005-06-14
System initialization of microcode-based memory built-in self-test Grant 6,874,111 - Adams , et al. March 29, 2	2005-03-29
Built-in Self Test System And Method For Two-dimensional Memory Redundancy Allocation App 20040225939 - Adams, R. Dean ; et al.	2004-11-11
Two-dimensional redundancy calculation App 20040093540 - Adams, R. Dean ; et al.	2004-05-13
Method and apparatus for testing multi-port memories App 20040006727 - Adams, R. Dean ; et al.	2004-01-08
Programmable memory built-in self-test combining microcode and finite state machine self-test Grant 6,651,201 - Adams , et al. November 18, 2	2003-11-18
Programable multi-port memory bist with compact microcode App 20030120974 - Adams, R. Dean ; et al.	2003-06-26
System for synchronizing execution by a processing element of threads within a process using a state indicator Grant 5,553,305 - Gregor , et al. September 3, 1	1996-09-03
Execution of storage-immediate and storage-storage instructions within cache buffer storage Grant 5,313,613 - Gregor May 17, 1	1994-05-17
Shared two level cache including apparatus for maintaining storage consistency Grant 5,276,848 - Gallagher , et al. January 4, 1	1994-01-04
System for execution of storage-immediate and storage-storage instructions within cache buffer storage Grant 5,226,169 - Gregor July 6, 1	1993-07-06
Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage Grant 5,023,776 - Gregor June 11, 1	1991-06-11
Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system Grant 4,924,466 - Gregor , et al. May 8, 1	1990-05-08

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