Greco; Stephen Edward

Patent Applications and Registrations

Patent applications and USPTO patent grants for Greco; Stephen Edward.The latest application filed is for "interconnect structure and process of making the same".

Company Profile

0.9.6

Greco; Stephen Edward - LaGrangeville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interconnect structure and process of making the same Grant 7,488,679 - Standaert , et al. February 10, 2	2009-02-10
Semiconductor structure having recess with conductive metal Grant 7,456,501 - Uzoh , et al. November 25, 2	2008-11-25
Interconnect Structure And Process Of Making The Same App 20080026568 - Standaert; Theodorus Eduardus ; et al.	2008-01-31
Customizing back end of the line interconnects Grant 7,300,825 - Greco , et al. November 27, 2	2007-11-27
Maintaining uniform CMP hard mask thickness Grant 7,253,098 - Chen , et al. August 7, 2	2007-08-07
Maintaining Uniform Cmp Hard Mask Thickness App 20060043590 - Chen; Steven Shyng-Tsong T. ; et al.	2006-03-02
Customizing back end of the line interconnects App 20050242442 - Greco, Nancy Anne ; et al.	2005-11-03
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,831,364 - Dalton , et al. December 14, 2	2004-12-14
Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect Grant 6,573,606 - Sambucetti , et al. June 3, 2	2003-06-03
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20030057414 - Dalton, Timothy Joseph ; et al.	2003-03-27
Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect App 20030001275 - Sambucetti, Carlos Juan ; et al.	2003-01-02
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,451,712 - Dalton , et al. September 17, 2	2002-09-17
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20020074659 - Dalton, Timothy Joseph ; et al.	2002-06-20
Method to selectively fill recesses with conductive metal Grant 6,140,234 - Uzoh , et al. October 31, 2	2000-10-31
Process for reducing pattern factor effects in CMP planarization Grant 5,928,960 - Greco , et al. July 27, 1	1999-07-27

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