Greco; Stephen E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Greco; Stephen E..The latest application filed is for "early overlay prediction and overlay-aware mask design".

Company Profile

1.50.42

Greco; Stephen E. - Lagrangeville NY
Greco; Stephen E. - Stamford CT
Greco; Stephen E - Lagrangeville NY
Greco; Stephen E. - Beacon NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multiple-depth trench interconnect technology at advanced semiconductor nodes Grant 10,169,525 - Greco , et al. J	2019-01-01
Early overlay prediction and overlay-aware mask design Grant 10,152,567 - Greco , et al. Dec	2018-12-11
Early Overlay Prediction And Overlay-aware Mask Design App 20180129774 - Greco; Stephen E. ; et al.	2018-05-10
Early overlay prediction and overlay-aware mask design Grant 9,940,429 - Greco , et al. April 10, 2	2018-04-10
Multiple-depth Trench Interconnect Technology At Advanced Semiconductor Nodes App 20170277823 - Greco; Stephen E. ; et al.	2017-09-28
Multiple-depth trench interconnect technology at advanced semiconductor nodes Grant 9,710,592 - Greco , et al. July 18, 2	2017-07-18
Interconnect level structures for confining stitch-induced via structures Grant 9,601,367 - Greco , et al. March 21, 2	2017-03-21
Integrated circuit structure with crack stop and method of forming same Grant 9,589,912 - Liang , et al. March 7, 2	2017-03-07
Integrated circuit structure with metal crack stop and methods of forming same Grant 9,589,911 - Liang , et al. March 7, 2	2017-03-07
Integrated Circuit Structure With Crack Stop And Method Of Forming Same App 20170062355 - Liang; Jim S. ; et al.	2017-03-02
Integrated Circuit Structure With Metal Crack Stop And Methods Of Forming Same App 20170062354 - Liang; Jim S. ; et al.	2017-03-02
Early Overlay Prediction And Overlay-aware Mask Design App 20160378904 - Greco; Stephen E. ; et al.	2016-12-29
Selective local metal cap layer formation for improved electromigration behavior Grant 9,455,186 - Angyal , et al. September 27, 2	2016-09-27
Stitch-derived via structures and methods of generating the same Grant 9,454,631 - Greco , et al. September 27, 2	2016-09-27
Dividing lithography exposure fields to improve semiconductor fabrication Grant 9,424,388 - Greco , et al. August 23, 2	2016-08-23
Selective local metal cap layer formation for improved electromigration behavior Grant 9,406,560 - Angyal , et al. August 2, 2	2016-08-02
Selective local metal cap layer formation for improved electromigration behavior Grant 9,385,038 - Angyal , et al. July 5, 2	2016-07-05
Dividing Lithography Exposure Fields To Improve Semiconductor Fabrication App 20160180003 - Greco; Stephen E. ; et al.	2016-06-23
Interconnect level structures for confining stitch-induced via structures Grant 9,373,538 - Greco , et al. June 21, 2	2016-06-21
Multiple-depth Trench Interconnect Technology At Advancedsemiconductor Nodes App 20160042114 - Greco; Stephen E. ; et al.	2016-02-11
Interconnect Level Structures For Confining Stitch-induced Via Structures App 20160027687 - Greco; Stephen E. ; et al.	2016-01-28
Stitch-derived Via Structures And Methods Of Generating The Same App 20150339422 - Greco; Stephen E. ; et al.	2015-11-26
Measuring metal line spacing in semiconductor devices Grant 9,157,980 - Dyer , et al. October 13, 2	2015-10-13
Selective Local Metal Cap Layer Formation For Improved Electromigration Behavior App 20150255343 - Angyal; Matthew S. ; et al.	2015-09-10
Selective Local Metal Cap Layer Formation For Improved Electromigration Behavior App 20150255342 - Angyal; Matthew S. ; et al.	2015-09-10
Selective Local Metal Cap Layer Formation For Improved Electromigration Behavior App 20150255398 - Angyal; Matthew S. ; et al.	2015-09-10
System and method of predicting problematic areas for lithography in a circuit design Grant 9,075,944 - Brunner , et al. July 7, 2	2015-07-07
Selective local metal cap layer formation for improved electromigration behavior Grant 9,076,847 - Angyal , et al. July 7, 2	2015-07-07
Reticle data decomposition for focal plane determination in lithographic processes Grant 9,058,457 - Greco , et al. June 16, 2	2015-06-16
Reticle Data Decomposition For Focal Plane Determination In Lithographic Processes App 20150143305 - Greco; Stephen E. ; et al.	2015-05-21
Interconnect Level Structures For Confining Stitch-induced Via Structures App 20140284813 - Greco; Stephen E. ; et al.	2014-09-25
Generation of design shapes for confining stitch-induced via structures Grant 8,806,393 - Greco , et al. August 12, 2	2014-08-12
Selective Local Metal Cap Layer Formation For Improved Electromigration Behavior App 20140203435 - Angyal; Matthew S. ; et al.	2014-07-24
Measuring Metal Line Spacing In Semiconductor Devices App 20140139236 - Dyer; Thomas W. ; et al.	2014-05-22
System And Method Of Predicting Problematic Areas For Lithography In A Circuit Design App 20130286370 - Brunner; Timothy A. ; et al.	2013-10-31
IC having viabar interconnection and related method Grant 8,492,268 - Chidambarrao , et al. July 23, 2	2013-07-23
System and method of predicting problematic areas for lithography in a circuit design Grant 8,484,586 - Brunner , et al. July 9, 2	2013-07-09
IC having viabar interconnection and related method Grant 8,299,622 - Chidambarrao , et al. October 30, 2	2012-10-30
System And Method Of Predicting Problematic Areas For Lithography In A Circuit Design App 20120254812 - BRUNNER; Timothy A. ; et al.	2012-10-04
System and method of predicting problematic areas for lithography in a circuit design Grant 8,239,789 - Brunner , et al. August 7, 2	2012-08-07
Ic Having Viabar Interconnection And Related Method App 20120164758 - Chidambarrao; Dureseti ; et al.	2012-06-28
Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design Grant 8,117,568 - Xiang , et al. February 14, 2	2012-02-14
Integrated circuit fuse Grant 8,053,862 - Greco November 8, 2	2011-11-08
System and method of predicting problematic areas for lithography in a circuit design Grant 8,001,495 - Brunner , et al. August 16, 2	2011-08-16
System And Method Of Predicting Problematic Areas For Lithography In A Circuit Design App 20110184715 - BRUNNER; Timothy A. ; et al.	2011-07-28
Via density change to improve wafer surface planarity Grant 7,949,981 - Greco May 24, 2	2011-05-24
Intersect area based ground rule for semiconductor design Grant 7,941,780 - Avanessian , et al. May 10, 2	2011-05-10
Laser fuse structures for high power applications Grant 7,701,035 - Greco , et al. April 20, 2	2010-04-20
Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design App 20100077372 - Xiang; Hua ; et al.	2010-03-25
Ic Having Viabar Interconnection And Related Method App 20100032846 - Chidambarrao; Dureseti ; et al.	2010-02-11
Via Density Change To Improve Wafer Surface Planarity App 20100031221 - Greco; Stephen E.	2010-02-04
Dry etchback of interconnect contacts Grant 7,645,700 - Standaert , et al. January 12, 2	2010-01-12
Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors Grant 7,612,371 - Ahsan , et al. November 3, 2	2009-11-03
Intersect Area Based Ground Rule For Semiconductor Design App 20090265673 - Avanessian; Albrik ; et al.	2009-10-22
System And Method Of Predicting Problematic Areas For Lithography In A Circuit Design App 20090265679 - Brunner; Timothy A. ; et al.	2009-10-22
Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via Grant 7,439,173 - Greco , et al. October 21, 2	2008-10-21
Integrated Circuit Fuse App 20080179709 - Greco; Stephen E.	2008-07-31
Integrated circuit fuse and method of opening Grant 7,390,615 - Greco June 24, 2	2008-06-24
Dynamic metal fill for correcting non-planar region Grant 7,368,302 - Greco May 6, 2	2008-05-06
Dry Etchback Of Interconnect Contacts App 20080088027 - STANDAERT; THEODORUSE ; et al.	2008-04-17
Increasing Electromigration Lifetime And Current Density In Ic Using Vertically Upwardly Extending Dummy Via App 20080026567 - Greco; Stephen E. ; et al.	2008-01-31
Dry etchback of interconnect contacts Grant 7,323,410 - Standaert , et al. January 29, 2	2008-01-29
Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via Grant 7,301,236 - Greco , et al. November 27, 2	2007-11-27
Structure To Monitor Arcing In The Processing Steps Of Metal Layer Build On Silicon-on-insulator Semiconductors App 20070164421 - Ahsan; Ishtiaq ; et al.	2007-07-19
Laser Fuse Structures For High Power Applications App 20070120232 - Greco; Stephen E. ; et al.	2007-05-31
Increasing Electromigration Lifetime And Current Densityin Ic Using Vertically Upwardly Extending Dummy Via App 20070087555 - Greco; Stephen E. ; et al.	2007-04-19
Dry Etchback Of Interconnect Contacts App 20070032055 - Standaert; Theodorus E. ; et al.	2007-02-08
Reliable low-k interconnect structure with hybrid dielectric Grant 7,135,398 - Fitzsimmons , et al. November 14, 2	2006-11-14
Dynamic Metal Fill For Correcting Non-planar Region App 20060246609 - GRECO; STEPHEN E.	2006-11-02
Method to generate porous organic dielectric Grant 7,101,784 - Clevenger , et al. September 5, 2	2006-09-05
Forming of local and global wiring for semiconductor product Grant 7,071,099 - Greco , et al. July 4, 2	2006-07-04
Method to generate porous organic dielectric App 20050200024 - Clevenger, Lawrence A. ; et al.	2005-09-15
Method to generate porous organic dielectric Grant 6,921,978 - Clevenger , et al. July 26, 2	2005-07-26
Reliable low-k interconnect structure with hybrid dielectric Grant 6,917,108 - Fitzsimmons , et al. July 12, 2	2005-07-12
Reliable low-k interconnect structure with hybrid dielectric App 20050023693 - Fitzsimmons, John A. ; et al.	2005-02-03
Integrated Circuit Fuse And Method Of Opening App 20040259035 - Greco, Stephen E.	2004-12-23
Method To Generate Porous Organic Dielectric App 20040224494 - Clevenger, Lawrence A. ; et al.	2004-11-11
Reliable low-k interconnect structure with hybrid dielectric App 20040094839 - Fitzsimmons, John A. ; et al.	2004-05-20
Method of forming planar Cu interconnects without chemical mechanical polishing App 20040094511 - Seo, Soon-Cheon ; et al.	2004-05-20
Fine-pitch device lithography using a sacrificial hardmask Grant 6,734,096 - Dalton , et al. May 11, 2	2004-05-11
Dual damascene flowable oxide insulation structure and metallic barrier Grant 6,727,589 - Greco , et al. April 27, 2	2004-04-27
Fine-pitch device lithography using a sacrificial hardmask App 20030134505 - Dalton, Timothy J. ; et al.	2003-07-17
Interim oxidation of silsesquioxane dielectric for dual damascene process App 20010036739 - Cook, Robert ; et al.	2001-11-01
Dual damascene flowable oxide insulation structure and metallic barrier App 20010000115 - Greco, Stephen E. ; et al.	2001-04-05
Integrated circuit having crack stop for interlevel dielectric layers Grant 6,091,131 - Cook , et al. July 18, 2	2000-07-18
Large scale IC personalization method employing air dielectric structure for extended conductor Grant 5,530,290 - Aitken , et al. June 25, 1	1996-06-25
Larce scale IC personalization method employing air dielectric structure for extended conductors Grant 5,444,015 - Aitken , et al. August 22, 1	1995-08-22
Chip interconnection having a breathable etch stop layer Grant 5,371,047 - Greco , et al. December 6, 1	1994-12-06
Method of forming conductive lines and studs Grant 4,997,746 - Greco , et al. March 5, 1	1991-03-05
Cross-linked polyalkenyl phenol based photoresist compositions Grant 4,600,683 - Greco , et al. July 15, 1	1986-07-15

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