Greco; Joseph R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Greco; Joseph R..The latest application filed is for "method to build vertical pnp in a bicmos technology with improved speed".

Company Profile

1.16.13

Greco; Joseph R. - South Burlington VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure Grant 10,211,324 - Greco , et al. Feb	2019-02-19
Method To Build Vertical Pnp In A Bicmos Technology With Improved Speed App 20180069105 - Greco; Joseph R. ; et al.	2018-03-08
Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure Grant 9,837,514 - Greco , et al. December 5, 2	2017-12-05
Method to build vertical PNP in a BiCMOS technology with improved speed Grant 9,735,259 - Greco , et al. August 15, 2	2017-08-15
Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure App 20160197167 - Greco; Joseph R. ; et al.	2016-07-07
Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming Grant 9,324,828 - Greco , et al. April 26, 2	2016-04-26
Vertical P-type, N-type, P-type (pnp) Junction Integrated Circuit (ic) Structure, And Methods Of Forming App 20160049492 - Greco; Joseph R. ; et al.	2016-02-18
Method to build vertical PNP in a BICMOS technology with improved speed App 20160049501 - Greco; Joseph R. ; et al.	2016-02-18
Electromagnetic electron reflector Grant 9,214,318 - Caprarola , et al. December 15, 2	2015-12-15
Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region Grant 8,492,294 - Greco , et al. July 23, 2	2013-07-23
Semiconductor-on-insulator Substrate And Structure Including Multiple Order Radio Frequency Harmonic Supressing Region App 20130005157 - Greco; Joseph R. ; et al.	2013-01-03
Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region Grant 8,299,537 - Greco , et al. October 30, 2	2012-10-30
Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure Grant 7,777,302 - Geiss , et al. August 17, 2	2010-08-17
Semiconductor-on-insulator Substrate And Structure Including Multiple Order Radio Ferquency Harmonic Supressing Region App 20100200927 - Greco; Joseph R. ; et al.	2010-08-12
Method for recycling of ion implantation monitor wafers Grant 7,732,303 - Codding , et al. June 8, 2	2010-06-08
Recycling of ion implantation monitor wafers Grant 7,700,488 - Codding , et al. April 20, 2	2010-04-20
Method For Recycling Of Ion Implantation Monitor Wafers App 20090197400 - Codding; Steven Ross ; et al.	2009-08-06
Recycling Of Ion Implantation Monitor Wafers App 20080171439 - Codding; Steven Ross ; et al.	2008-07-17
Method Of Controlling Grain Size In A Polysilicon Layer And In Semiconductor Devices Having Polysilicon Structure App 20070284694 - Geiss; Peter J. ; et al.	2007-12-13
Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures Grant 7,247,924 - Geiss , et al. July 24, 2	2007-07-24
Discontinuous dielectric interface for bipolar transistors Grant 7,008,852 - Ballantine , et al. March 7, 2	2006-03-07
Discontinuous dielectric interface for bipolar transistors Grant 6,939,771 - Ballantine , et al. September 6, 2	2005-09-06
Discontinuous dielectric interface for bipolar transistors App 20050093053 - Ballantine, Arne W. ; et al.	2005-05-05
Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures App 20040084754 - Geiss, Peter J. ; et al.	2004-05-06
Discontinuous dielectric interface for bipolar transistors App 20040056327 - Ballantine, Arne W. ; et al.	2004-03-25
Discontinuous dielectric interface for bipolar transistors Grant 6,703,283 - Ballantine , et al. March 9, 2	2004-03-09
Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures Grant 6,682,992 - Geiss , et al. January 27, 2	2004-01-27
Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures App 20030216013 - Geiss, Peter J. ; et al.	2003-11-20

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