Graves-Abe; Troy L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Graves-Abe; Troy L..The latest application filed is for "architecture and implementation of cortical system, and fabricating an architecture using 3d wafer scale integration".

Company Profile

4.33.32

Graves-Abe; Troy L. - Wappingers Falls NY
Graves-Abe; Troy L. - Wappinger Falls NY
Graves-Abe; Troy L. - Hopewell Junction NY US
Graves-Abe; Troy L - Wappingers Falls NY US
Graves-Abe; Troy L. - Wapingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration Grant 10,613,754 - Berger , et al.	2020-04-07
Architecture And Implementation Of Cortical System, And Fabricating An Architecture Using 3d Wafer Scale Integration App 20200042182 - Berger; Daniel G. ; et al.	2020-02-06
Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration Grant 10,503,402 - Berger , et al. Dec	2019-12-10
Forming multi-sized through-silicon-via (TSV) structures Grant 10,296,698 - Farooq , et al.	2019-05-21
Implant after through-silicon via (TSV) etch to getter mobile ions Grant 10,170,337 - Collins , et al. J	2019-01-01
Forming Multi-sized Through-silicon-via (tsv) Structures App 20180165402 - Farooq; Mukta G. ; et al.	2018-06-14
Architecture And Implementation Of Cortical System, And Fabricating An Architecture Using 3d Wafer Scale Integration App 20180136846 - Berger; Daniel G. ; et al.	2018-05-17
Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration Grant 9,886,193 - Berger , et al. February 6, 2	2018-02-06
Implant After Through-silicon Via (tsv) Etch To Getter Mobile Ions App 20170200620 - Collins; Christopher ; et al.	2017-07-13
Wafer bonding using boron and nitrogen based bonding stack Grant 9,640,514 - Lin , et al. May 2, 2	2017-05-02
Architecture And Implementation Of Cortical System, And Fabricating An Architecture Using 3d Wafer Scale Integration App 20160334991 - Berger; Daniel G. ; et al.	2016-11-17
Structure and method to determine through silicon via build integrity Grant 9,476,927 - Graves-Abe , et al. October 25, 2	2016-10-25
3-D integration using multi stage vias Grant 9,263,324 - Farooq , et al. February 16, 2	2016-02-16
Bottom-up plating of through-substrate vias Grant 9,257,336 - Farooq , et al. February 9, 2	2016-02-09
Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures Grant 9,252,133 - Collins , et al. February 2, 2	2016-02-02
Via structure for three-dimensional circuit integration Grant 9,214,435 - Farooq , et al. December 15, 2	2015-12-15
Structure And Method To Determine Through Silicon Via Build Integrity App 20150204932 - Graves-Abe; Troy L. ; et al.	2015-07-23
Sidewalls of electroplated copper interconnects Grant 9,060,457 - Farooq , et al. June 16, 2	2015-06-16
Sidewalls of electroplated copper interconnects Grant 9,055,703 - Farooq , et al. June 9, 2	2015-06-09
Sidewalls of electroplated copper interconnects Grant 9,040,407 - Farooq , et al. May 26, 2	2015-05-26
Through-silicon-via with sacrificial dielectric line Grant 8,975,910 - Graves-Abe , et al. March 10, 2	2015-03-10
Bottom-up Plating Of Through-substrate Vias App 20150056804 - Farooq; Mukta G. ; et al.	2015-02-26
Bottom-up plating of through-substrate vias Grant 8,956,973 - Farooq , et al. February 17, 2	2015-02-17
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via Grant 8,951,906 - Farooq , et al. February 10, 2	2015-02-10
Via Structure For Three-dimensional Circuit Integration App 20150035169 - Farooq; Mukta G. ; et al.	2015-02-05
Anticipatory implant for TSV Grant 8,927,427 - Graves-Abe , et al. January 6, 2	2015-01-06
Electrical Leakage Reduction In Stacked Integrated Circuits Having Through-silicon-via (tsv) Structures App 20150004749 - Collins; Christopher N. ; et al.	2015-01-01
Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures Grant 8,907,494 - Collins , et al. December 9, 2	2014-12-09
Method Of Forming A Through-silicon Via Utilizing A Metal Contact Pad In A Back-end-of-line Wiring Level To Fill The Through-silicon Via App 20140342552 - Farooq; Mukta G. ; et al.	2014-11-20
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via Grant 8,889,542 - Farooq , et al. November 18, 2	2014-11-18
Anticipatory Implant For Tsv App 20140319694 - Graves-Abe; Troy L. ; et al.	2014-10-30
3-D integration using multi stage vias Grant 8,853,857 - Farooq , et al. October 7, 2	2014-10-07
Stacked Integrated Circuit App 20140264756 - Collins; Christopher N. ; et al.	2014-09-18
Method Of Forming A Through-silicon Via Utilizing A Metal Contact Pad In A Back-end-of-line Wiring Level To Fill The Through-silicon Via App 20140227870 - Farooq; Mukta G. ; et al.	2014-08-14
Sidewalls of electroplated copper interconnects Grant 8,791,005 - Farooq , et al. July 29, 2	2014-07-29
TSV pillar as an interconnecting structure Grant 8,691,691 - Farooq , et al. April 8, 2	2014-04-08
3-d Integration Using Multi Stage Vias App 20140073134 - Farooq; Mukta G. ; et al.	2014-03-13
Prevention Of Thru-substrate Via Pistoning Using Highly Doped Copper Alloy Seed Layer App 20140061915 - Collins; Christopher N. ; et al.	2014-03-06
Sidewalls Of Electroplated Copper Interconnects App 20140027911 - Farooq; Mukta G. ; et al.	2014-01-30
Sidewalls Of Electroplated Copper Interconnects App 20140027912 - Farooq; Mukta G. ; et al.	2014-01-30
Sidewalls Of Electroplated Copper Interconnects App 20140027296 - Farooq; Mukta G. ; et al.	2014-01-30
Sidewalls Of Electroplated Copper Interconnects App 20130334691 - Farooq; Mukta G. ; et al.	2013-12-19
Via Structure For Three-Dimensional Circuit Integration App 20130307160 - Farooq; Mukta G. ; et al.	2013-11-21
Through-silicon-via With Sacrificial Dielectric Line App 20130285694 - Graves-Abe; Troy L. ; et al.	2013-10-31
Bottom-up Plating Of Through-substrate Vias App 20130260556 - Farooq; Mukta G. ; et al.	2013-10-03
Alignment marks to enable 3D integration Grant 8,546,961 - Farooq , et al. October 1, 2	2013-10-01
Non-conformal hardmask deposition for through silicon etch Grant 8,476,168 - Graves-Abe , et al. July 2, 2	2013-07-02
Tsv Pillar As An Interconnecting Structure App 20130026606 - Farooq; Mukta G. ; et al.	2013-01-31
3-D Integration using Multi Stage Vias App 20120280395 - Farooq; Mukta G. ; et al.	2012-11-08
Non-conformal Hardmask Deposition For Through Silicon Etch App 20120190204 - Graves-Abe; Troy L. ; et al.	2012-07-26
Alignment Marks To Enable 3d Integration App 20120175789 - Farooq; Mukta G. ; et al.	2012-07-12