| Patent | Date |
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Semiconductor devices having silicon/germanium active regions with different germanium concentrations
Grant 11,031,406 - Smith , et al. June 8, 2 | 2021-06-08 |
Semiconductor devices including Si/Ge active regions with different Ge concentrations
Grant 10,522,555 - Smith , et al. Dec | 2019-12-31 |
Semiconductor Devices Including Si/ge Active Regions With Different Ge Concentrations
App 20190312041 - Smith; Elliot John ; et al. | 2019-10-10 |
Methods Of Forming Semiconductor Devices Having Silicon/germanium Active Regions With Different Germanium Concentrations
App 20190312042 - Smith; Elliot John ; et al. | 2019-10-10 |
Semiconductor devices and manufacturing techniques for reduced aspect ratio of neighboring gate electrode lines
Grant 10,224,251 - Moll , et al. | 2019-03-05 |
Semiconductor Devices And Manufacturing Techniques For Reduced Aspect Ratio Of Neighboring Gate Electrode Lines
App 20190043764 - Moll; Hans-Peter ; et al. | 2019-02-07 |
Methods of forming a gate cap layer above a replacement gate structure
Grant 10,199,479 - Grasshoff , et al. Fe | 2019-02-05 |
Semiconductor device comprising trench isolation
Grant 10,103,067 - Baars , et al. October 16, 2 | 2018-10-16 |
High-voltage Transistor Device
App 20170338343 - Baudot; Sylvain Henri ; et al. | 2017-11-23 |
Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
Grant 9,412,600 - van Bentum , et al. August 9, 2 | 2016-08-09 |
Method Of Forming A Semiconductor Structure Including A Ferroelectric Material And Semiconductor Structure Including A Ferroelectric Transistor
App 20160064228 - van Bentum; Ralf ; et al. | 2016-03-03 |
Methods Of Forming A Gate Cap Layer Above A Replacement Gate Structure
App 20160056263 - Grasshoff; Gunter ; et al. | 2016-02-25 |
Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure
Grant 8,932,930 - Beyer , et al. January 13, 2 | 2015-01-13 |
Methods of forming conductive structures using a spacer erosion technique
Grant 8,791,017 - Grasshoff July 29, 2 | 2014-07-29 |
Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
App 20130181265 - Grasshoff; Gunter ; et al. | 2013-07-18 |
Enhancing Integrity Of A High-k Gate Stack By Protecting A Liner At The Gate Bottom During Gate Head Exposure
App 20130157432 - BEYER; Sven ; et al. | 2013-06-20 |
Methods of Forming Conductive Structures Using a Spacer Erosion Technique
App 20130109174 - Grasshoff; Gunter | 2013-05-02 |
Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure
Grant 8,329,549 - Beyer , et al. December 11, 2 | 2012-12-11 |
Using high-k dielectrics as highly selective etch stop materials in semiconductor devices
Grant 8,198,166 - Kammler , et al. June 12, 2 | 2012-06-12 |
Etch methods for semiconductor device fabrication
Grant 8,133,814 - Laufer , et al. March 13, 2 | 2012-03-13 |
Method of forming CMOS device having gate insulation layers of different type and thickness
Grant 8,021,942 - Wei , et al. September 20, 2 | 2011-09-20 |
Using High-k Dielectrics As Highly Selective Etch Stop Materials In Semiconductor Devices
App 20110024805 - Kammler; Thorsten ; et al. | 2011-02-03 |
Enhancing Integrity Of A High-k Gate Stack By Protecting A Liner At The Gate Bottom During Gate Head Exposure
App 20100136762 - Beyer; Sven ; et al. | 2010-06-03 |
CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor
Grant 7,723,174 - Waite , et al. May 25, 2 | 2010-05-25 |
Transistor Having A Strained Channel Region Caused By Hydrogen-induced Lattice Deformation
App 20100025742 - Beyer; Sven ; et al. | 2010-02-04 |
Cmos Device Comprising Mos Transistors With Recessed Drain And Source Areas And A Si/ge Material In The Drain And Source Areas Of The Pmos Transistor
App 20090321843 - Waite; Andrew ; et al. | 2009-12-31 |
Cmos Device Having Gate Insulation Layers Of Different Type And Thickness And A Method Of Forming The Same
App 20090057769 - Wei; Andy ; et al. | 2009-03-05 |
Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process
Grant 7,381,622 - Hellmich , et al. June 3, 2 | 2008-06-03 |
Method For Forming Embedded Strained Drain/source Regions Based On A Combined Spacer And Cavity Etch Process
App 20070232006 - Hellmich; Andreas ; et al. | 2007-10-04 |
Signal layer for generating characteristic optical plasma emissions
Grant 7,005,305 - Grasshoff , et al. February 28, 2 | 2006-02-28 |
Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process
Grant 6,969,676 - Schwan , et al. November 29, 2 | 2005-11-29 |
Advanced process control for a manufacturing process of a plurality of products with minimized control degradation after re-initialization upon occurrence of reset events
Grant 6,879,871 - Grasshoff , et al. April 12, 2 | 2005-04-12 |
Methods for producing a highly doped electrode for a field effect transistor
Grant 6,875,676 - Wieczorek , et al. April 5, 2 | 2005-04-05 |
System and method for wafer-based controlled patterning of features with critical dimensions
Grant 6,838,010 - Grasshoff , et al. January 4, 2 | 2005-01-04 |
Method of forming a substrate contact for an SOI semiconductor device
App 20040241917 - Schwan, Christoph ; et al. | 2004-12-02 |
Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process
App 20040241984 - Schwan, Christoph ; et al. | 2004-12-02 |
Plasma parameter control using learning data
App 20040118516 - Grasshoff, Gunter ; et al. | 2004-06-24 |
Signal layer for generating characteristic optical plasma emissions
App 20040106284 - Grasshoff, Gunter ; et al. | 2004-06-03 |
Method and an apparatus for determining the dimension of a feature by varying a resolution determining parameter
App 20040084619 - Hartig, Carsten ; et al. | 2004-05-06 |
Die corner alignment structure
Grant 6,724,096 - Werner , et al. April 20, 2 | 2004-04-20 |
Highly doped electrode for a field effect transistor and method for producing same
App 20040016974 - Wieczorek, Karsten ; et al. | 2004-01-29 |
Advanced process control for a manufacturing process of a plurality of products with minimized control degradation after re-initialization upon occurrence of reset events
App 20030204278 - Grasshoff, Gunter ; et al. | 2003-10-30 |
System and method for wafer-based controlled patterning of features with critical dimensions
App 20030015493 - Grasshoff, Gunter ; et al. | 2003-01-23 |
Die corner alignment structure
App 20020185753 - Werner, Thomas ; et al. | 2002-12-12 |
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