Gould; Scott W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gould; Scott W..The latest application filed is for "method and apparatus for manufacturing diamond shaped chips".

Company Profile

0.22.13

Gould; Scott W. - South Burlington VT
Gould; Scott W - South Burlington VT
Gould, Scott W. - So. Burlington VT
Gould; Scott W. - Burlington VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for manufacturing diamond shaped chips Grant 7,961,932 - Allen , et al. June 14, 2	2011-06-14
Electrostatic discharge failure avoidance through interaction between floorplanning and power routing Grant 7,496,877 - Huber , et al. February 24, 2	2009-02-24
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20080018872 - Allen; Robert J. ; et al.	2008-01-24
Method and apparatus for manufacturing diamond shaped chips Grant 7,289,659 - Allen , et al. October 30, 2	2007-10-30
Method and apparatus for performing power routing on a voltage island within an integrated circuit chip Grant 7,234,124 - Chen , et al. June 19, 2	2007-06-19
Electrostatic discharge failure avoidance through interaction between floorplanning and power routing App 20070035900 - Huber; Andrew D. ; et al.	2007-02-15
Nested voltage island architecture Grant 7,131,074 - Bednar , et al. October 31, 2	2006-10-31
Macro design techniques to accommodate chip level wiring and circuit placement across the macro Grant 7,096,436 - Bednar , et al. August 22, 2	2006-08-22
Method and apparatus for performing power routing on a voltage island within an integrated circuit chip App 20050120322 - Chen, Bing ; et al.	2005-06-02
Voltage island chip implementation Grant 6,883,152 - Bednar , et al. April 19, 2	2005-04-19
Macro design techniques to accommodate chip level wiring and circuit placement across the macro Grant 6,883,155 - Bednar , et al. April 19, 2	2005-04-19
Method and apparatus for performing power routing on a voltage island within an integrated circuit chip Grant 6,861,753 - Chen , et al. March 1, 2	2005-03-01
Macro design techniques to accommodate chip level wiring and circuit placement across the macro App 20050039153 - Bednar, Thomas R. ; et al.	2005-02-17
Nested Voltage Island Architecture App 20050010887 - Bednar, Thomas R. ; et al.	2005-01-13
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20040258294 - Allen, Robert J. ; et al.	2004-12-23
Voltage island chip implementation App 20040243958 - Bednar, Thomas R. ; et al.	2004-12-02
Power reduction by stage in integrated circuit Grant 6,825,711 - Cohn , et al. November 30, 2	2004-11-30
Voltage island chip implementation Grant 6,820,240 - Bednar , et al. November 16, 2	2004-11-16
Power Reduction By Stage In Integrated Circuit App 20040217805 - Cohn, John M. ; et al.	2004-11-04
Low-power critical error rate communications controller Grant 6,802,033 - Bertin , et al. October 5, 2	2004-10-05
Voltage island design planning Grant 6,779,163 - Bednar , et al. August 17, 2	2004-08-17
Voltage island design planning App 20040060024 - Bednar, Thomas R. ; et al.	2004-03-25
Voltage island chip implementation App 20040060023 - Bednar, Thomas R. ; et al.	2004-03-25
Macro design techniques to accommodate chip level wiring and circuit placement across the macro App 20030204829 - Bednar, Thomas R. ; et al.	2003-10-30
Method and system of modifying integrated circuit power rails Grant 6,598,206 - Darden , et al. July 22, 2	2003-07-22
Macro design techniques to accommodate chip level wiring and circuit placement across the macro Grant 6,543,040 - Bednar , et al. April 1, 2	2003-04-01
Method of integrated circuit design by selection of noise tolerant gates Grant 6,490,708 - Cohn , et al. December 3, 2	2002-12-03
Method and system of modifying integrated circuit power rails App 20020170020 - Darden, Laura R. ; et al.	2002-11-14
Method of integrated circuit design by selection of noise tolerant gates App 20020133791 - Cohn, John M. ; et al.	2002-09-19
Method and apparatus for preventing thermal failure in a semiconductor device through redundancy Grant 6,425,092 - Evans , et al. July 23, 2	2002-07-23
Simulation based power optimization Grant 6,397,170 - Dean , et al. May 28, 2	2002-05-28
Toggle based application specific core methodology Grant 6,237,132 - Dean , et al. May 22, 2	2001-05-22
Programmable array interconnect network Grant 5,631,578 - Clinton , et al. May 20, 1	1997-05-20
Method and system for enhanced drive in programmmable gate arrays Grant 5,552,721 - Gould September 3, 1	1996-09-03
Wiring layout design method and system for integrated circuits Grant 5,341,310 - Gould , et al. August 23, 1	1994-08-23

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