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Patent applications and USPTO patent grants for Gou; Tatsuo.The latest application filed is for "method and program for designing semiconductor integrated circuit, method and program for supporting design of semiconductor integrated circuit, and method and program for calculating wiring parasitic capacitance".
Patent | Date |
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Interconnect structure of semiconductor integrated circuit, and design method and device therefor Grant 7,913,221 - Miyashita , et al. March 22, 2 | 2011-03-22 |
Method for designing semiconductor integrated circuits having air gaps. Grant 7,698,671 - Fujii , et al. April 13, 2 | 2010-04-13 |
Method And Program For Designing Semiconductor Integrated Circuit, Method And Program For Supporting Design Of Semiconductor Integrated Circuit, And Method And Program For Calculating Wiring Parasitic Capacitance App 20080120583 - Fujii; Tsutomu ;   et al. | 2008-05-22 |
Interconnect structure of semiconductor integrated circuit, and design method and device therefor App 20080097641 - Miyashita; Hirofumi ;   et al. | 2008-04-24 |
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