Goth; George R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Goth; George R..The latest application filed is for "reduction of chemical mechanical planarization (cmp) scratches with sacrificial dielectric polish stop".

Company Profile

0.17.2

Goth; George R. - Poughkeepsie NY
Goth; George R. - Jericho VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polish stop Grant 6,967,375 - Gehres , et al. November 22, 2	2005-11-22
Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polish stop App 20050151192 - Gehres, Rainer E. ; et al.	2005-07-14
Methods to control the threshold voltage of a deep trench corner device Grant 6,518,145 - Alsmeier , et al. February 11, 2	2003-02-11
Self-aligned corner Vt enhancement with isolation channel stop by ion implantation App 20020179997 - Goth, George R. ; et al.	2002-12-05
Self-aligned metal process for integrated circuit metallization Grant 4,758,528 - Goth , et al. * July 19, 1	1988-07-19
Lateral device structures using self-aligned fabrication techniques Grant 4,743,565 - Goth , et al. May 10, 1	1988-05-10
Method of making shallow junction complementary vertical bipolar transistor pair Grant 4,719,185 - Goth January 12, 1	1988-01-12
Method of forming self-aligned P contact Grant 4,717,678 - Goth January 5, 1	1988-01-05
Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor Grant 4,704,368 - Goth , et al. November 3, 1	1987-11-03
Lateral device structures using self-aligned fabrication techniques Grant 4,688,073 - Goth , et al. August 18, 1	1987-08-18
Planarization process for organic filling of deep trenches Grant 4,665,007 - Cservak , et al. May 12, 1	1987-05-12
Metal silicide channel stoppers for integrated circuits and method for making the same Grant 4,589,193 - Goth , et al. May 20, 1	1986-05-20
Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices Grant 4,549,927 - Goth , et al. October 29, 1	1985-10-29
Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes Grant 4,541,168 - Galie , et al. September 17, 1	1985-09-17
Trench etch process for dielectric isolation Grant 4,534,826 - Goth , et al. August 13, 1	1985-08-13
Lateral device structures using self-aligned fabrication techniques Grant 4,508,579 - Goth , et al. April 2, 1	1985-04-02
Self-aligned metal process for integrated circuit metallization Grant 4,400,865 - Goth , et al. August 30, 1	1983-08-30
Forming adjacent impurity regions in a semiconductor by oxide masking Grant 4,151,010 - Goth April 24, 1	1979-04-24
Wafer Transport System Grant 3,731,823 - Goth May 8, 1	1973-05-08

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