| Patent | Date |
|---|
Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas
Grant 6,298,551 - Wojnarowski , et al. October 9, 2 | 2001-10-09 |
Interface structures for electronic devices
Grant 6,046,410 - Wojnarowski , et al. April 4, 2 | 2000-04-04 |
Structure for thin film capacitors
Grant 5,973,908 - Saia , et al. October 26, 1 | 1999-10-26 |
Structure for protecting air bridges on semiconductor chips from damage
Grant 5,757,072 - Gorowitz , et al. May 26, 1 | 1998-05-26 |
Fabrication method for thin film capacitors
Grant 5,736,448 - Saia , et al. April 7, 1 | 1998-04-07 |
Stacking of three dimensional high density interconnect modules with metal edge contacts
Grant 5,699,234 - Saia , et al. December 16, 1 | 1997-12-16 |
Method for fabricating a stack of two dimensional circuit modules
Grant 5,657,537 - Saia , et al. August 19, 1 | 1997-08-19 |
Flexible multilayer thin film capacitors
Grant 5,576,925 - Gorowitz , et al. November 19, 1 | 1996-11-19 |
Structure for protecting air bridges on semiconductor chips from damage
Grant 5,561,085 - Gorowitz , et al. October 1, 1 | 1996-10-01 |
Fabrication and structures of circuit modules with flexible interconnect layers
Grant 5,527,741 - Cole , et al. June 18, 1 | 1996-06-18 |
Method for protecting gallium arsenide mmic air bridge structures
Grant 5,524,339 - Gorowitz , et al. June 11, 1 | 1996-06-11 |
Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures
Grant 5,401,687 - Cole , et al. March 28, 1 | 1995-03-28 |
Method for enhancement of semiconductor device contact pads
Grant 5,391,516 - Wojnarowski , et al. February 21, 1 | 1995-02-21 |
Wafer level integration and testing
Grant 5,366,906 - Wojnarowski , et al. November 22, 1 | 1994-11-22 |
Combustion control for producing low NO.sub.x emissions through use of flame spectroscopy
Grant 5,257,496 - Brown , et al. November 2, 1 | 1993-11-02 |
Power field effect devices having small cell size and low contact resistance
Grant 4,998,151 - Korman , et al. March 5, 1 | 1991-03-05 |
Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
Grant 4,824,802 - Brown , et al. April 25, 1 | 1989-04-25 |
Method for tapered dry etching
Grant 4,522,681 - Gorowitz , et al. June 11, 1 | 1985-06-11 |
Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys
Grant 4,444,618 - Saia , et al. April 24, 1 | 1984-04-24 |
Electrostatic-fluidized bed coating of wire
Grant 4,188,413 - Lupinski , et al. February 12, 1 | 1980-02-12 |
Apparatus for electrostatic deposition on a running conductor
Grant 4,100,883 - Lupinski , et al. July 18, 1 | 1978-07-18 |
Powder coatable polyester composition and electrical conductor coated therewith
Grant 4,074,006 - Boldebuck , et al. February 14, 1 | 1978-02-14 |
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