Gopal; Rama S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Gopal; Rama S..The latest application filed is for "memory load to load fusing".
- Gopal; Rama S. - Austin TX
| Patent | Date |
|---|---|
| Memory load to load fusing Grant 10,956,155 - Kitchin , et al. March 23, 2 | 2021-03-23 |
| Memory Load To Load Fusing App 20190278603 - KITCHIN; Paul E. ; et al. | 2019-09-12 |
| Memory load to load fusing Grant 10,372,452 - Kitchin , et al. | 2019-08-06 |
| Memory load and arithmetic load unit (ALU) fusing Grant 10,275,217 - Gopal , et al. | 2019-04-30 |
| Memory Load And Arithmetic Load Unit (alu) Fusing App 20180267775 - GOPAL; Rama S. ; et al. | 2018-09-20 |
| Memory Load To Load Fusing App 20180267800 - KITCHIN; Paul E. ; et al. | 2018-09-20 |
| Multi-core shared page miss handler Grant 9,921,968 - Bryant , et al. March 20, 2 | 2018-03-20 |
| Multi-core shared page miss handler Grant 9,921,967 - Bryant , et al. March 20, 2 | 2018-03-20 |
| Multi-core shared page miss handler Grant 9,892,059 - Bryant , et al. February 13, 2 | 2018-02-13 |
| Multi-core shared page miss handler Grant 9,892,056 - Bryant , et al. February 13, 2 | 2018-02-13 |
| Multi-core Shared Page Miss Handler App 20170147506 - BRYANT; CHRISTOPHER D. ; et al. | 2017-05-25 |
| Multi-core Shared Page Miss Handler App 20170116134 - BRYANT; CHRISTOPHER D. ; et al. | 2017-04-27 |
| Multi-core Shared Page Miss Handler App 20170109293 - BRYANT; CHRISTOPHER D. ; et al. | 2017-04-20 |
| Multi-core Shared Page Miss Handler App 20130031332 - Bryant; Christopher D. ; et al. | 2013-01-31 |
| Cache memory subsystem including a fixed latency R/W pipeline Grant 7,251,710 - Isaac , et al. July 31, 2 | 2007-07-31 |
| Load store unit with replay mechanism Grant 7,165,167 - Filippo , et al. January 16, 2 | 2007-01-16 |
| Load store unit with replay mechanism App 20040255101 - Filippo, Michael A. ; et al. | 2004-12-16 |
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