Goo; Jung-Suk

Patent Applications and Registrations

Patent applications and USPTO patent grants for Goo; Jung-Suk.The latest application filed is for "method and apparatus for simulating junction capacitance of a tucked transistor device".

Company Profile

2.35.22

Goo; Jung-Suk - Los Altos CA
- Los Altos CA US
Goo; Jung-Suk - Stanford CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for simulating gate capacitance of a tucked transistor device Grant 8,818,785 - Goo , et al. August 26, 2	2014-08-26
Dynamic random access memory (DRAM) cells and methods for fabricating the same Grant 8,618,592 - Cho , et al. December 31, 2	2013-12-31
Dynamic random access memory (DRAM) cells and methods for fabricating the same Grant 08618592 -	2013-12-31
Silicon-on-insulator ("SOI") transistor test structure for measuring body-effect Grant 8,586,981 - Chen , et al. November 19, 2	2013-11-19
Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device App 20130117001 - Goo; Jung-Suk ; et al.	2013-05-09
Method and Apparatus for Simulating Junction Capacitance of a Tucked Transistor Device App 20130117002 - Goo; Jung-Suk ; et al.	2013-05-09
Body tie test structure for accurate body effect measurement Grant 8,293,606 - Madhavan , et al. October 23, 2	2012-10-23
Method for robust statistical semiconductor device modeling Grant 8,275,596 - Wason , et al. September 25, 2	2012-09-25
Two-step simulation methodology for aging simulations Grant 8,099,269 - Topaloglu , et al. January 17, 2	2012-01-17
Dynamic Random Access Memory (dram) Cells And Methods For Fabricating The Same App 20110204429 - CHO; Hyun-Jin ; et al.	2011-08-25
Dynamic random access memory (DRAM) cells and methods for fabricating the same Grant 7,977,172 - Cho , et al. July 12, 2	2011-07-12
Integrated circuit system with MOS device Grant 7,932,103 - Subba , et al. April 26, 2	2011-04-26
Body Tie Test Structure For Accurate Body Effect Measurement App 20110086484 - MADHAVAN; Sriram ; et al.	2011-04-14
Field effect transistor having increased carrier mobility Grant 7,923,785 - Xiang , et al. April 12, 2	2011-04-12
Body tie test structure for accurate body effect measurement Grant 7,880,229 - Madhavan , et al. February 1, 2	2011-02-01
Method for adjusting a transistor model for increased circuit simulation accuracy Grant 7,761,823 - Goo , et al. July 20, 2	2010-07-20
Dynamic Random Access Memory (dram) Cells And Methods For Fabricating The Same App 20100144106 - CHO; Hyun-Jin ; et al.	2010-06-10
Shallow trench isolation process and structure with minimized strained silicon consumption Grant 7,732,336 - Xiang , et al. June 8, 2	2010-06-08
Body Tie Test Structure For Accurate Body Effect Measurement App 20090101976 - MADHAVAN; Sriram ; et al.	2009-04-23
Two-step Simulation Methodology For Aging Simulations App 20090094013 - TOPALOGLU; Rasit O. ; et al.	2009-04-09
Shallow trench isolation process and structure with minimized strained silicon consumption Grant 7,462,549 - Xiang , et al. December 9, 2	2008-12-09
Method for adjusting a transistor model for increased circuit simulation accuracy App 20080286887 - Goo; Jung-Suk ; et al.	2008-11-20
Shallow Trench Isolation Process And Structure With Minimized Strained Silicon Consumption App 20080213952 - Xiang; Qi ; et al.	2008-09-04
Integrated Circuit System With Mos Device App 20080204052 - Subba; Niraj ; et al.	2008-08-28
Silicon-on-insulator ("SOI") transistor test structure for measuring body-effect App 20080185581 - Chen; Qiang ; et al.	2008-08-07
Method for robust statistical semiconductor device modeling App 20080141189 - Wason; Vineet ; et al.	2008-06-12
CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric Grant 7,176,531 - Xiang , et al. February 13, 2	2007-02-13
Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication Grant 7,170,084 - Xiang , et al. January 30, 2	2007-01-30
Method of fabricating an integrated circuit channel region Grant 7,138,302 - Xiang , et al. November 21, 2	2006-11-21
Formation of finFET using a sidewall epitaxial layer Grant 7,078,299 - Maszara , et al. July 18, 2	2006-07-18
Strained silicon semiconductor on insulator MOSFET Grant 7,033,869 - Xiang , et al. April 25, 2	2006-04-25
Silicon on insulator substrate having improved thermal conductivity and method of its formation Grant 7,015,078 - Xiang , et al. March 21, 2	2006-03-21
Strained silicon MOSFET having improved thermal conductivity and method for its fabrication Grant 7,012,007 - Goo , et al. March 14, 2	2006-03-14
Shallow trench isolation process using oxide deposition and anneal Grant 6,962,857 - Ngo , et al. November 8, 2	2005-11-08
Method of growing as a channel region to reduce source/drain junction capacitance Grant 6,955,969 - Djomehri , et al. October 18, 2	2005-10-18
Semiconductor on insulator MOSFET having strained silicon channel Grant 6,943,087 - Xiang , et al. September 13, 2	2005-09-13
Replacement gate strained silicon finFET process Grant 6,936,516 - Goo , et al. August 30, 2	2005-08-30
Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift Grant 6,929,992 - Djomehri , et al. August 16, 2	2005-08-16
Shallow trench isolation process and structure with minimized strained silicon consumption App 20050151222 - Xiang, Qi ; et al.	2005-07-14
Method of fabricating a strained silicon channel FinFET App 20050153486 - Xiang, Qi ; et al.	2005-07-14
Semiconductor device having a thick strained silicon layer and method of its formation Grant 6,902,991 - Xiang , et al. June 7, 2	2005-06-07
Strained silicon MOSFETs having improved thermal dissipation Grant 6,900,143 - Pan , et al. May 31, 2	2005-05-31
Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure Grant 6,872,613 - Xiang , et al. March 29, 2	2005-03-29
Method For Integrating Metals Having Different Work Functions To Fom Cmos Gates Having A High-k Gate Dielectric And Related Structure App 20050054149 - Xiang, Qi ; et al.	2005-03-10
Method of growing as a channel region to reduce source/drain junction capicitance App 20050048743 - Djomehri, Ihsan J. ; et al.	2005-03-03
Formation Of Finfet Using A Sidewall Epitaxial Layer App 20050048727 - Maszara, Witold P. ; et al.	2005-03-03
Field effect transistor having increased carrier mobility App 20050040477 - Xiang, Qi ; et al.	2005-02-24
Depletion to avoid cross contamination Grant 6,858,503 - Ngo , et al. February 22, 2	2005-02-22
FinFET device incorporating strained silicon in the channel region Grant 6,800,910 - Lin , et al. October 5, 2	2004-10-05
Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication Grant 6,756,276 - Xiang , et al. June 29, 2	2004-06-29
Semiconductor device having a thick strained silicon layer and method of its formation App 20040087114 - Xiang, Qi ; et al.	2004-05-06
Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Grant 6,730,576 - Wang , et al. May 4, 2	2004-05-04
Finfet having improved carrier mobility and method of its formation App 20040061178 - Lin, Ming-Ren ; et al.	2004-04-01

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