Goo; Doo-Hoon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Goo; Doo-Hoon.The latest application filed is for "nanoimprint lithography template and method of fabricating semiconductor device using the same".

Company Profile

0.11.12

Goo; Doo-Hoon - Hwaseong-si KR
Goo; Doo-Hoon - Gyeonggi-do KR
Goo; Doo-Hoon - Suwon-si KR
Goo; Doo-Hoon - Busan KR
Goo, Doo-Hoon - Busan-City KR
Goo; Doo Hoon - Pusan KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming fine patterns using a nanoimprint lithography Grant 8,287,792 - Lee , et al. October 16, 2	2012-10-16
Semiconductor memory devices including offset bit lines Grant 8,013,374 - Goo , et al. September 6, 2	2011-09-06
Nanoimprint Lithography Template and Method of Fabricating Semiconductor Device Using the Same App 20100230864 - Park; Chang-min ; et al.	2010-09-16
Methods of forming fine patterns using a nanoimprint lithography App 20100190340 - Lee; Jeong-Hoon ; et al.	2010-07-29
Semiconductor Memory Devices Including Offset Bit Lines App 20090218609 - Goo; Doo-Hoon ; et al.	2009-09-03
Semiconductor memory devices including offset active regions Grant 7,547,936 - Goo , et al. June 16, 2	2009-06-16
Semiconductor memory device having high electrical performance and mask and photolithography friendliness Grant 7,375,390 - Lee , et al. May 20, 2	2008-05-20
Method of forming trench in semiconductor device Grant 7,259,065 - Goo , et al. August 21, 2	2007-08-21
DRAM devices having an increased density layout Grant 7,221,014 - Goo , et al. May 22, 2	2007-05-22
Semiconductor Memory Device Having High Electrical Performance And Mask And Photolithography Friendliness App 20070108491 - Lee; Jung-Hyeon ; et al.	2007-05-17
Semiconductor memory device having high electrical performance and mask and photolithography friendliness Grant 7,176,512 - Lee , et al. February 13, 2	2007-02-13
Methods and apparatus for aligning a wafer in which multiple light beams are used to scan alignment marks Grant 7,068,371 - Goo June 27, 2	2006-06-27
Method of forming self-aligned contact pads of non-straight type semiconductor memory device Grant 7,064,051 - Lee , et al. June 20, 2	2006-06-20
Semiconductor memory devices including offset active regions App 20060076599 - Goo; Doo-Hoon ; et al.	2006-04-13
Dram devices having an increased density layout App 20050269615 - Goo, Doo-hoon ; et al.	2005-12-08
Method of forming trench in semiconductor device App 20050266646 - Goo, Doo-hoon ; et al.	2005-12-01
Method of forming self-aligned contact pads of non-straight type semiconductor memory device App 20050070080 - Lee, Eun-Mi ; et al.	2005-03-31
Semiconductor memory device having high electrical performance and mask and photolithography friendliness App 20050035387 - Lee, Jung-Hyeon ; et al.	2005-02-17
Wafer edge exposing apparatus App 20040189971 - Goo, Doo-Hoon ; et al.	2004-09-30
Single aperture optical system for photolithography systems Grant 6,757,052 - Goo , et al. June 29, 2	2004-06-29
Methods and apparatus for aligning a wafer in which multiple light beams are used to scan alignment marks App 20040002172 - Goo, Doo-Hoon	2004-01-01
Single aperture optical system for photolithography systems App 20030086070 - Goo, Doo-Hoon ; et al.	2003-05-08
Apparatus and method for forming a film on a tape substrate Grant 6,147,033 - Youm , et al. November 14, 2	2000-11-14

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