| Patent | Date |
|---|
Memory cell with redundant carbon nanotube
Grant 9,842,991 - Nelson , et al. December 12, 2 | 2017-12-12 |
Carbon nanotube memory cell with enhanced current control
Grant 9,165,633 - Golke , et al. October 20, 2 | 2015-10-20 |
Memory Cell With Redundant Carbon Nanotube
App 20140264251 - Nelson; David K. ; et al. | 2014-09-18 |
Carbon Nanotube Memory Cell With Enhanced Current Control
App 20140241052 - Golke; Keith W. ; et al. | 2014-08-28 |
SRAM split write control for a delay element
Grant 7,693,001 - Golke , et al. April 6, 2 | 2010-04-06 |
SRAM Split Write Control for a Delay Element
App 20080106955 - Golke; Keith W. ; et al. | 2008-05-08 |
Simulating a dose rate event in a circuit design
Grant 7,322,015 - Liu , et al. January 22, 2 | 2008-01-22 |
SRAM split write control for a delay element
App 20070279964 - Golke; Keith W. ; et al. | 2007-12-06 |
Radiation-hardened memory element with multiple delay elements
App 20070242537 - Golke; Keith W. ; et al. | 2007-10-18 |
Single event transient immune antenna diode circuit
App 20070162880 - Carlson; Roy M. ; et al. | 2007-07-12 |
Method and system for analyzing single event upset in semiconductor devices
App 20070096754 - Johnson; Michael T. ; et al. | 2007-05-03 |
Voltage divider and method for minimizing higher than rated voltages
App 20070063758 - Allard; Thaddeus A. ; et al. | 2007-03-22 |
Dose rate simulation
App 20060145086 - Liu; Harry H.L. ; et al. | 2006-07-06 |
Full rail drive enhancement to differential SEU hardening circuit while loading data
Grant 6,909,637 - Nelson , et al. June 21, 2 | 2005-06-21 |
Full rail drive enhancement to differential seu hardening circuit while loading data
App 20040100320 - Nelson, David K. ; et al. | 2004-05-27 |
Full rail drive enhancement to differential SEU hardening circuit
Grant 6,608,512 - Ta , et al. August 19, 2 | 2003-08-19 |
Full Rail Drive Enhancement To Differential Seu Hardening Circuit
App 20030122602 - Ta, Theodore T. ; et al. | 2003-07-03 |
Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
Grant 6,300,666 - Fechner , et al. October 9, 2 | 2001-10-09 |
SEU hardening circuit
Grant 6,058,041 - Golke , et al. May 2, 2 | 2000-05-02 |
CMOS output driver with p-channel substrate tracking for cold spare capability
Grant 5,867,039 - Golke February 2, 1 | 1999-02-02 |
Random access memory cell resistant to radiation induced upsets
Grant 5,631,863 - Fechner , et al. May 20, 1 | 1997-05-20 |
Fuse status detection circuit
Grant 4,837,520 - Golke , et al. June 6, 1 | 1989-06-06 |
Memory circuit enchancement to stablize the signal lines with additional capacitance
Grant 4,761,571 - Golke , et al. August 2, 1 | 1988-08-02 |
High sensitivity variable capacitance transducer
Grant 4,420,790 - Golke , et al. December 13, 1 | 1983-12-13 |
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