| Patent | Date |
|---|
Integrated circuit with self-aligned line and via
Grant 8,766,454 - Lim , et al. July 1, 2 | 2014-07-01 |
Method of manufacturing 3-D spiral stacked inductor on semiconductor material
Grant 7,721,414 - Sia , et al. May 25, 2 | 2010-05-25 |
Integrated Circuit With Self-aligned Line And Via
App 20070075371 - Lim; Yeow Kheng ; et al. | 2007-04-05 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
Grant 7,119,010 - Lim , et al. October 10, 2 | 2006-10-10 |
Extended poly buffer STI scheme
Grant 7,060,573 - Lim , et al. June 13, 2 | 2006-06-13 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
Grant 6,998,682 - Chan , et al. February 14, 2 | 2006-02-14 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
App 20050208712 - Chan, Yeen Tat ; et al. | 2005-09-22 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
Grant 6,905,919 - Chan , et al. June 14, 2 | 2005-06-14 |
Method of manufacturing 3-D spiral stacked inductor on semiconductor material
App 20050057335 - Sia, Choon-Beng ; et al. | 2005-03-17 |
Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
App 20050023608 - Chan, Yeen Tat ; et al. | 2005-02-03 |
Dual silicon-on-insulator device wafer die
Grant 6,849,928 - Cha , et al. February 1, 2 | 2005-02-01 |
3-D spiral stacked inductor on semiconductor material
Grant 6,841,847 - Sia , et al. January 11, 2 | 2005-01-11 |
3-D spiral stacked inductor on semiconductor material
App 20040041234 - Sia, Choon-Beng ; et al. | 2004-03-04 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
App 20030197279 - Lim, Yeow Kheng ; et al. | 2003-10-23 |
Method for buffer STI scheme with a hard mask layer as an oxidation barrier
Grant 6,613,649 - Lim , et al. September 2, 2 | 2003-09-02 |
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
Grant 6,613,652 - Lim , et al. September 2, 2 | 2003-09-02 |
Shallow trench isolation using TEOS cap and polysilicon pullback
Grant 6,613,648 - Lim , et al. September 2, 2 | 2003-09-02 |
Dual silicon-on-insulator device wafer die
App 20030107083 - Cha, Randall Cher Liang ; et al. | 2003-06-12 |
Method for buffer STI scheme with a hard mask layer as an oxidation barrier
App 20030104675 - Lim, Seng-Keong Victor ; et al. | 2003-06-05 |
Dual silicon-on-insulator device wafer die
Grant 6,558,994 - Cha , et al. May 6, 2 | 2003-05-06 |
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
App 20020132448 - Lim, Yeow Kheng ; et al. | 2002-09-19 |
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
App 20020127834 - Lim, Yeow Kheng ; et al. | 2002-09-12 |
Dual silicon-on-insulator device wafer die
App 20020127816 - Cha, Randall Cher Liang ; et al. | 2002-09-12 |
Extended poly buffer STI scheme
App 20020094648 - Lim, Victor Seng Keong ; et al. | 2002-07-18 |
Method to achieve STI planarization
Grant 6,403,484 - Lim , et al. June 11, 2 | 2002-06-11 |
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
Grant 6,380,084 - Lim , et al. April 30, 2 | 2002-04-30 |
Method to prevent CU dishing during damascene formation
Grant 6,376,376 - Lim , et al. April 23, 2 | 2002-04-23 |
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