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Patent applications and USPTO patent grants for Gogineni; Sireesha.The latest application filed is for "integrated circuit package with glass spacer".
Patent | Date |
---|---|
Integrated Circuit Package With Glass Spacer App 20220254757 - Guo; Mao ;   et al. | 2022-08-11 |
Integrated circuit package with glass spacer Grant 11,393,788 - Guo , et al. July 19, 2 | 2022-07-19 |
Integrated Circuit Package With Glass Spacer App 20210280558 - Guo; Mao ;   et al. | 2021-09-09 |
Stacked Die Semiconductor Package Spacer Die App 20200350227 - Gogineni; Sireesha ;   et al. | 2020-11-05 |
Bowl Shaped Pad App 20200118954 - CAI; Yuhong ;   et al. | 2020-04-16 |
Pad Design For Thermal Fatigue Resistance And Interconnect Joint Reliability App 20200118955 - GOGINENI; Sireesha ;   et al. | 2020-04-16 |
Packaged integrated circuit device with cantilever structure Grant 10,490,516 - Meyers , et al. Nov | 2019-11-26 |
Eliminating Die Shadow Effects By Dummy Die Beams For Solder Joint Reliability Improvement App 20180323172 - GUO; Mao ;   et al. | 2018-11-08 |
Semiconductor Chip Package With Cavity App 20180190776 - Gogineni; Sireesha ;   et al. | 2018-07-05 |
Packaged Integrated Circuit Device With Cantilever Structure App 20180138133 - Meyers; John G. ;   et al. | 2018-05-17 |
Packaged integrated circuit device with cantilever structure Grant 9,871,007 - Meyers , et al. January 16, 2 | 2018-01-16 |
Crack Resistant Electronic Device Package Substrates App 20170186701 - Cai; Yuhong ;   et al. | 2017-06-29 |
Packaged Integrated Circuit Device With Cantilever Structure App 20170092602 - Meyers; John G. ;   et al. | 2017-03-30 |
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