Goel; Prabhakar
Patent Applications and Registrations
Patent applications and USPTO patent grants for Goel; Prabhakar.The latest application filed is for "method of electrically testing a packaging structure having n interconnected integrated circuit chips".
- Goel; Prabhakar - Poughkeepsie NY
| Patent | Date |
|---|---|
| Method of electrically testing a packaging structure having N interconnected integrated circuit chips Grant 4,504,784 - Goel , et al. March 12, 1 | 1985-03-12 |
| Method of electrically testing a packaging structure having n interconnected integrated circuit chips Grant 4,494,066 - Goel , et al. January 15, 1 | 1985-01-15 |
| Level sensitive scan design (LSSD) system Grant 4,293,919 - Dasgupta , et al. October 6, 1 | 1981-10-06 |
| Logic chip test system with path oriented decision making test pattern generator Grant 4,204,633 - Goel May 27, 1 | 1980-05-27 |
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