Godiwala; Nitin D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Godiwala; Nitin D..The latest application filed is for "system and method for scheduling message transmission and processing in a digital data network".

Company Profile

0.11.2

Godiwala; Nitin D. - Costa Mesa CA
Godiwala; Nitin D. - Boylston MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for scheduling message transmission and processing in a digital data network Grant 7,295,557 - Clayton , et al. November 13, 2	2007-11-13
System and method for regulating message flow in a digital data network Grant 7,283,471 - Gutierrez , et al. October 16, 2	2007-10-16
System and method for scheduling message transmission and processing in a digital data network App 20040208181 - Clayton, Shawn A. ; et al.	2004-10-21
System and method for scheduling message transmission and processing in a digital data network Grant 6,795,442 - Clayton , et al. September 21, 2	2004-09-21
Distributed switch and connection control arrangement and method for digital communications network Grant 6,791,948 - Desnoyers , et al. September 14, 2	2004-09-14
System and method for regulating message flow in a digital data network App 20030174647 - Gutierrez, Maria C. ; et al.	2003-09-18
Bus interface slicing mechanism allowing for a control/data path slice Grant 6,077,306 - Metzger , et al. June 20, 2	2000-06-20
Fault management scheme for a cache memory Grant 5,629,950 - Godiwala , et al. May 13, 1	1997-05-13
Intelligent snoopy bus arbiter Grant 5,555,382 - Thaller , et al. September 10, 1	1996-09-10
Method and apparatus for forming an exchange address for a system with different size caches Grant 5,553,258 - Godiwala , et al. September 3, 1	1996-09-03
Scheme for error handling in a computer system Grant 5,361,267 - Godiwala , et al. November 1, 1	1994-11-01
Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system Grant 5,319,766 - Thaller , et al. June 7, 1	1994-06-07
Multisignal synchronizer with shared last stage Grant 5,274,628 - Thaller , et al. December 28, 1	1993-12-28

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