Goddard; Michael D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Goddard; Michael D..The latest application filed is for "program counter update mechanism".

Company Profile

0.15.0

Goddard; Michael D. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Program counter update mechanism Grant 6,351,801 - Christie , et al. February 26, 2	2002-02-26
Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core Grant 5,903,772 - White , et al. May 11, 1	1999-05-11
Instruction queue scanning using opcode identification Grant 5,896,518 - Yao , et al. April 20, 1	1999-04-20
Superscalar microprocessor including flag operand renaming and forwarding apparatus Grant 5,805,853 - White , et al. September 8, 1	1998-09-08
Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions Grant 5,796,973 - Witt , et al. August 18, 1	1998-08-18
Microcode patching apparatus and method Grant 5,796,974 - Goddard , et al. August 18, 1	1998-08-18
Resynchronization of a superscalar processor Grant 5,764,938 - White , et al. June 9, 1	1998-06-09
Floating point processing unit with forced arithmetic results Grant 5,748,516 - Goddard , et al. May 5, 1	1998-05-05
Floating point stack and exchange instruction Grant 5,696,955 - Goddard , et al. December 9, 1	1997-12-09
Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions Grant 5,689,672 - Witt , et al. November 18, 1	1997-11-18
Resynchronization of a superscalar processor Grant 5,649,225 - White , et al. July 15, 1	1997-07-15
Superscalar microprocessor including flag operand renaming and forwarding apparatus Grant 5,632,023 - White , et al. May 20, 1	1997-05-20
Apparatus and method for instruction queue scanning Grant 5,630,082 - Yao , et al. May 13, 1	1997-05-13
Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments Grant 5,574,928 - White , et al. November 12, 1	1996-11-12
Exception handling processor for handling first and second level exceptions with reduced exception latency Grant 5,237,700 - Johnson , et al. August 17, 1	1993-08-17

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