loadpatents
name:-0.0025191307067871
name:-0.022606134414673
name:-0.009429931640625
GLOBALFOUNDARIES INC. Patent Filings

GLOBALFOUNDARIES INC.

Patent Applications and Registrations

Patent applications and USPTO patent grants for GLOBALFOUNDARIES INC..The latest application filed is for "overlapping contacts for semiconductor device".

Company Profile
9.18.1
  • GLOBALFOUNDARIES INC. - Grand Cayman KY
  • GLOBALFOUNDARIES Inc - Grand Cayman KY US
  • GLOBALFOUNDARIES Inc. - Cayman Islands N/A KY
  • GLOBALFOUNDARIES INC. - Grand Caymen KY US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuits having single state memory reference cells and methods for operating the same
Grant 10,460,782 - Huang Oc
2019-10-29
Contact structures and methods of making the contact structures
Grant 10,381,354 - Chanemougame , et al. A
2019-08-13
On-chip calibration circuit and method with half-step resolution
Grant 10,382,049 - Hunt-Schroeder , et al. A
2019-08-13
Integrated graphene detectors with waveguides
Grant 10,374,106 - Jacob
2019-08-06
Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
Grant 10,332,803 - Xie , et al.
2019-06-25
Gate pickup method using metal selectivity
Grant 10,242,867 - Bouche , et al.
2019-03-26
Switched-capacitor charge pump with reduced diode threshold voltage and on state resistance
Grant 10,236,768 - Koe
2019-03-19
FINFET fin height control
Grant 9,530,654 - Licausi December 27, 2
2016-12-27
Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof
Grant 9,530,833 - Triyoso , et al. December 27, 2
2016-12-27
Heterojunction bipolar transistor with improved performance and breakdown voltage
Grant 9,368,608 - Camillo-Castillo , et al. June 14, 2
2016-06-14
Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures
Grant 9,343,589 - Adkisson , et al. May 17, 2
2016-05-17
FinFET fabrication method
Grant 9,123,772 - Wu , et al. September 1, 2
2015-09-01
Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures
Grant 9,099,393 - Ando , et al. August 4, 2
2015-08-04
Methods of forming a semiconductor device with low-k spacers and the resulting device
Grant 9,064,948 - Cai , et al. June 23, 2
2015-06-23
Integrating optimal planar and three-dimensional semiconductor design layouts
Grant 8,966,423 - Jain , et al. February 24, 2
2015-02-24
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
Grant 8,940,633 - Cai , et al. January 27, 2
2015-01-27
Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions
Grant 8,765,542 - Patzer , et al. July 1, 2
2014-07-01
Overlapping Contacts For Semiconductor Device
App 20130241070 - Engel; Brett H. ;   et al.
2013-09-19
Body tie test structure for accurate body effect measurement
Grant 8,293,606 - Madhavan , et al. October 23, 2
2012-10-23

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