loadpatents
name:-0.0003669261932373
name:-0.024137020111084
name:-0.0012109279632568
Glascock, II; Homer H. Patent Filings

Glascock, II; Homer H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Glascock, II; Homer H..The latest application filed is for "package for parallel subelement semiconductor devices".

Company Profile
0.22.0
  • Glascock, II; Homer H. - Millis MA
  • Glascock, II; Homer H. - Scotia NY
  • Glascock, II; Homer H. - Schenectady NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Package for parallel subelement semiconductor devices
Grant 5,473,193 - Temple , et al. December 5, 1
1995-12-05
Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
Grant 5,209,390 - Temple , et al. May 11, 1
1993-05-11
Method for forming semiconductor electrical contacts using metal foil and thermocompression bonding
Grant 5,206,186 - Neugebauer , et al. April 27, 1
1993-04-27
Direct thermocompression bonding for thin electronic power chips
Grant 5,184,206 - Neugebauer , et al. February 2, 1
1993-02-02
Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
Grant 5,135,890 - Temple , et al. August 4, 1
1992-08-04
Method of packaging a semiconductor chip in a low inductance package
Grant 5,105,536 - Neugebauer , et al. April 21, 1
1992-04-21
Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
Grant 5,103,290 - Temple , et al. April 7, 1
1992-04-07
Direct bonded symmetric-metallic-laminate/substrate structures
Grant 5,100,740 - Neugebauer , et al. March 31, 1
1992-03-31
Method of bonding a silicon package for a power semiconductor device
Grant 5,034,044 - Glascock, II * July 23, 1
1991-07-23
High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip
Grant 5,028,987 - Neugebauer , et al. July 2, 1
1991-07-02
Method of making direct bonded wafers having a void free interface
Grant 4,939,101 - Black , et al. July 3, 1
1990-07-03
Multi-chip interconnection package
Grant 4,901,136 - Neugebauer , et al. February 13, 1
1990-02-13
Flexible glass fiber mat bonding method
Grant 4,828,597 - Glascock, II , et al. May 9, 1
1989-05-09
Temperature compensated piezoelectric transducer assembly
Grant 4,825,117 - Thomas, III , et al. April 25, 1
1989-04-25
Multilayer circuit board fabricated from silicon
Grant 4,803,450 - Burgess , et al. February 7, 1
1989-02-07
Silicon packages for power semiconductor devices
Grant 4,745,455 - Glascock, II , et al. May 17, 1
1988-05-17
Thyristor packaging system
Grant 4,574,299 - Glascock, II , et al. March 4, 1
1986-03-04
Low loss, multilevel silicon circuit board
Grant 4,541,035 - Carlson , et al. September 10, 1
1985-09-10
Method of thermo-compression diffusion bonding together metal surfaces
Grant 4,444,352 - Glascock, II , et al. April 24, 1
1984-04-24
Cooled semiconductor power module including structured strain buffers without dry interfaces
Grant 4,392,153 - Glascock, II , et al. July 5, 1
1983-07-05
Ultrasonic bond testing of semiconductor devices
Grant 4,366,713 - Gilmore , et al. January 4, 1
1983-01-04
Fluid cooled solar powered photovoltaic cell
Grant 4,361,717 - Gilmore , et al. November 30, 1
1982-11-30

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