| Patent | Date |
|---|
Circuit for detection of predominant data in a memory cell
Grant 11,043,248 - Noel , et al. June 22, 2 | 2021-06-22 |
3d Memory Device Comprising Sram Type Memory Cells With Adjustable Back-bias
App 20210167072 - MAKOSIEJ; Adam ; et al. | 2021-06-03 |
Memory circuit
Grant 10,910,040 - Noel , et al. February 2, 2 | 2021-02-02 |
Memory circuit capable of implementing calculation operations
Grant 10,811,087 - Noel , et al. October 20, 2 | 2020-10-20 |
Partitioned memory circuit capable of implementing calculation operations
Grant 10,803,927 - Noel , et al. October 13, 2 | 2020-10-13 |
3D SRAM circuit with double gate transistors with improved layout
Grant 10,741,565 - Andrieu , et al. A | 2020-08-11 |
Circuit For Detection Of Predominant Data In A Memory Cell
App 20200227098 - NOEL; Jean-Philippe ; et al. | 2020-07-16 |
3d Integrated Circuit Random-access Memory
App 20200185392 - MAKOSIEJ; Adam ; et al. | 2020-06-11 |
Device and method for writing data to a resistive memory
Grant 10,559,355 - Harrand , et al. Feb | 2020-02-11 |
3d Sram Circuit With Double Gate Transistors With Improved Layout
App 20190312039 - Andrieu; Francois ; et al. | 2019-10-10 |
Memory Circuit
App 20190198094 - Noel; Jean-Philippe ; et al. | 2019-06-27 |
Memory circuit capable of implementing calculation operations
App 20190189199 - Noel; Jean-Philippe ; et al. | 2019-06-20 |
Partitioned Memory Circuit Capable Of Implementing
App 20190189198 - Noel; Jean-Philippe ; et al. | 2019-06-20 |
Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof
Grant 10,297,319 - Giraud , et al. | 2019-05-21 |
Sram Cell
App 20180277197 - Noel; Jean-Philippe ; et al. | 2018-09-27 |
Integrated circuit comprising transistors with different threshold voltages
Grant 9,911,737 - Giraud , et al. March 6, 2 | 2018-03-06 |
Unipolar Resistive Memory
App 20170316825 - Giraud; Bastien ; et al. | 2017-11-02 |
Device with SRAM memory cells including means for polarizing wells of memory cell transistors
Grant 9,542,996 - Thomas , et al. January 10, 2 | 2017-01-10 |
Programmable-resistance non-volatile memory
Grant 9,508,434 - Benoist , et al. November 29, 2 | 2016-11-29 |
Method for controlling an integrated circuit
Grant 9,479,168 - Giraud , et al. October 25, 2 | 2016-10-25 |
Device and method for writing data to a resistive memory
Grant 9,449,688 - Thomas , et al. September 20, 2 | 2016-09-20 |
Memory Device With Memory Cells Sram (static Random Access Memories) And Controlling The Polarization Of Boxes Of Transistors Of The Memory Cells
App 20160078924 - THOMAS; Olivier ; et al. | 2016-03-17 |
Device And Method For Writing Data To A Resistive Memory
App 20160071588 - Harrand; Michel ; et al. | 2016-03-10 |
Device And Method For Writing Data To A Resistive Memory
App 20160071589 - Thomas; Olivier ; et al. | 2016-03-10 |
Memoire Non Volatile A Resistance Programmable
App 20160027509 - BENOIST; Thomas-Medhi ; et al. | 2016-01-28 |
Integrated Circuit Comprising Transistors With Different Threshold Voltages
App 20150287722 - Giraud; Bastien ; et al. | 2015-10-08 |
Transistor with coupled gate and ground plane
Grant 9,136,366 - Giraud , et al. September 15, 2 | 2015-09-15 |
Method for generating a topography of an FDSOI integrated circuit
Grant 9,092,590 - Giraud , et al. July 28, 2 | 2015-07-28 |
Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well
Grant 9,093,499 - Noel , et al. July 28, 2 | 2015-07-28 |
Integrated circuit comprising a clock tree cell
Grant 9,000,840 - Thonnart , et al. April 7, 2 | 2015-04-07 |
Self-contained integrated circuit including adjacent cells of different types
Grant 8,969,967 - Noel , et al. March 3, 2 | 2015-03-03 |
Integrated circuit comprising a clock tree cell
Grant 8,937,505 - Giraud , et al. January 20, 2 | 2015-01-20 |
Method For Controlling An Integrated Circuit
App 20140292374 - Giraud; Bastien ; et al. | 2014-10-02 |
Transistor with coupled gate and ground plane
App 20140231916 - Giraud; Bastien ; et al. | 2014-08-21 |
Integrated Circuit Comprising A Clock Tree Cell
App 20140176216 - Thonnart; Yvain ; et al. | 2014-06-26 |
Integrated Circuit Comprising A Clock Tree Cell
App 20140176228 - Giraud; Bastien ; et al. | 2014-06-26 |
Method For Generating A Topography Of An Fdsoi Integrated Circuit
App 20140173544 - Giraud; Bastien ; et al. | 2014-06-19 |
Self-contained Integrated Circuit Including Adjacent Cells Of Different Types
App 20140077300 - Noel; Jean-Philippe ; et al. | 2014-03-20 |
Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same
Grant 8,482,070 - Flatresse , et al. July 9, 2 | 2013-07-09 |
Integrated Circuit Using Fdsoi Technology, With Well Sharing And Means For Biasing Oppositely Doped Ground Planes Present In A Same Well
App 20130089978 - Noel; Jean-Philippe ; et al. | 2013-04-11 |
SRAM memory cell with double gate transistors provided means to improve the write margin
Grant 8,320,198 - Thomas , et al. November 27, 2 | 2012-11-27 |
Sram Memory Cell With Double Gate Transistors Provided With Means To Improve The Write Margin
App 20100315889 - Thomas; Olivier ; et al. | 2010-12-16 |
Asymmetrical SRAM cell with 4 double-gate transistors
Grant 7,733,688 - Giraud , et al. June 8, 2 | 2010-06-08 |
Asymmetrical SRAM cell with 4 double-gate transistors
App 20080298118 - Giraud; Bastien ; et al. | 2008-12-04 |
| 