Gillis; Pamela S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gillis; Pamela S..The latest application filed is for "dense register array for enabling scan out observation of both l1 and l2 latches".

Company Profile

0.12.11

Gillis; Pamela S. - Jericho VT
Gillis; Pamela S. - Essex Junction VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dense register array for enabling scan out observation of both L1 and L2 latches Grant 8,423,844 - Gillis , et al. April 16, 2	2013-04-16
Method and apparatus for increased effectiveness of delay and transition fault testing Grant 8,381,050 - Gillis , et al. February 19, 2	2013-02-19
Method to test hold path faults using functional clocking Grant 8,230,283 - Gillis , et al. July 24, 2	2012-07-24
Dense Register Array For Enabling Scan Out Observation Of Both L1 And L2 Latches App 20120179944 - Gillis; Pamela S. ; et al.	2012-07-12
Hold transition fault model and test generation method Grant 8,181,135 - Iyengar , et al. May 15, 2	2012-05-15
Method To Test Hold Path Faults Using Functional Clocking App 20110154141 - Gillis; Pamela S. ; et al.	2011-06-23
Method And Apparatus For Increased Effectiveness Of Delay And Transistion Fault Testing App 20110121838 - Gillis; Pamela S. ; et al.	2011-05-26
Hold Transition Fault Model and Test Generation Method App 20110055650 - Iyengar; Vikram ; et al.	2011-03-03
Partial good integrated circuit and method of testing same Grant 7,478,301 - Farnsworth, III , et al. January 13, 2	2009-01-13
Partial Good Integrated Circuit And Method Of Testing Same App 20080209289 - Farnsworth; Leonard O. ; et al.	2008-08-28
Partial Good Integrated Circuit And Method Of Testing Same App 20080010571 - Farnsworth; Leonard O. III ; et al.	2008-01-10
Partial good integrated circuit and method of testing same Grant 7,305,600 - Farnsworth, III , et al. December 4, 2	2007-12-04
Method and circuit using boundary scan cells for design library analysis Grant 7,281,182 - Gillis , et al. October 9, 2	2007-10-09
Method And Circuit Using Boundary Scan Cells For Design Library Analysis App 20060190784 - Gillis; Pamela S. ; et al.	2006-08-24
Parametric testing for high pin count ASIC Grant 7,010,733 - Bassett , et al. March 7, 2	2006-03-07
Partial good integrated circuit and method of testing same App 20050047224 - Farnsworth, Leonard O. III ; et al.	2005-03-03
Method of electrically blowing fuses under control of an on-chip tester interface apparatus Grant 6,768,694 - Anand , et al. July 27, 2	2004-07-27
Parametric testing for high pin count ASIC App 20040073856 - Bassett, Robert W. ; et al.	2004-04-15
Method Of Electrically Blowing Fuses Under Control Of An On-chip Tester Interface Apparatus App 20040066695 - Anand, Darren L. ; et al.	2004-04-08
Self test method and device for dynamic voltage screen functionality improvement Grant 6,656,751 - Andersen , et al. December 2, 2	2003-12-02
Self test method and device for dynamic voltage screen functionality improvement App 20030090295 - Andersen, John E. ; et al.	2003-05-15

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