Ghosh; Sonia

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ghosh; Sonia.The latest application filed is for "static random access memory (sram) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and sram bit cell array circuits".

Company Profile

2.11.8

Ghosh; Sonia - San Diego CA
Ghosh; Sonia - Fishkill NY
Ghosh; Sonia - Karnataka IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Static Random Access Memory (sram) Bit Cell Circuits With A Minimum Distance Between A Storage Circuit Active Region And A Read Port Circuit Active Region To Reduce Area And Sram Bit Cell Array Circuits App 20220102360 - Biradar; Rahul ; et al.	2022-03-31
Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits Grant 11,289,495 - Biradar , et al. March 29, 2	2022-03-29
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods Grant 11,251,123 - Sharma , et al. February 15, 2	2022-02-15
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods Grant 11,222,846 - Sharma , et al. January 11, 2	2022-01-11
Determining A Voltage And/or Frequency For A Performance Mode App 20210255243 - GHOSH; Sonia ; et al.	2021-08-19
Determining a voltage and/or frequency for a performance mode Grant 11,092,646 - Ghosh , et al. August 17, 2	2021-08-17
Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories Grant 10,916,275 - Ghosh , et al. February 9, 2	2021-02-09
Efficient sense amplifier shifting for memory redundancy Grant 9,905,316 - Ghosh , et al. February 27, 2	2018-02-27
Efficient Sense Amplifier Shifting For Memory Redundancy App 20180033495 - Ghosh; Sonia ; et al.	2018-02-01
Timing Circuit For Memories App 20180012649 - GHOSH; Sonia ; et al.	2018-01-11
Timing circuit for memories Grant 9,858,988 - Ghosh , et al. January 2, 2	2018-01-02
Overlapping precharge and data write Grant 9,685,210 - Ghosh , et al. June 20, 2	2017-06-20
Device resulting from printing minimum width semiconductor features at non-minimum pitch Grant 9,484,300 - Ghosh , et al. November 1, 2	2016-11-01
Printing Minimum Width Features At Non-minimum Pitch And Resulting Device App 20160093565 - GHOSH; Sonia ; et al.	2016-03-31
Printing minimum width semiconductor features at non-minimum pitch and resulting device Grant 9,263,349 - Ghosh , et al. February 16, 2	2016-02-16
Printing Minimum Width Features At Non-minimum Pitch And Resulting Device App 20150130026 - GHOSH; Sonia ; et al.	2015-05-14
Design Structures And Methods For Extraction Of Device Channel Width App 20150102826 - MANN; Randy ; et al.	2015-04-16
Fast cyclic decoder circuit for FIFO/LIFO data buffer Grant 8,238,187 - Jain , et al. August 7, 2	2012-08-07
Fast Cyclic Decoder Circuit for FIFO/LIFO Data Buffer App 20120026819 - Jain; Animesh ; et al.	2012-02-02

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