Ghazavi; Parviz

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ghazavi; Parviz.The latest application filed is for "method of forming split gate memory cells with thinned side edge tunnel oxide".

Company Profile

4.8.6

Ghazavi; Parviz - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming split gate memory cells with thinned side edge tunnel oxide Grant 11,362,218 - Kim , et al. June 14, 2	2022-06-14
Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide App 20210399127 - Kim; Jinho ; et al.	2021-12-23
Method of making embedded memory device with silicon-on-insulator substrate Grant 11,183,506 - Kim , et al. November 23, 2	2021-11-23
Method of forming split gate memory cells with thinned tunnel oxide Grant 11,018,147 - Kim , et al. May 25, 2	2021-05-25
Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate App 20200395370 - Kim; Jinho ; et al.	2020-12-17
Method of making embedded memory device with silicon-on-insulator substrate Grant 10,790,292 - Kim , et al. September 29, 2	2020-09-29
Method of Making Embedded Memory Device With Silicon-On-Insulator Substrate App 20190348427 - Kim; Jinho ; et al.	2019-11-14
Method of forming memory array and logic devices Grant 9,673,208 - Kim , et al. June 6, 2	2017-06-06
Method Of Forming Memory Array And Logic Devices App 20170103991 - KIM; JINHO ; et al.	2017-04-13
Flash memory system using memory cell as source line pull down circuit Grant 9,564,238 - Bai , et al. February 7, 2	2017-02-07
Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates Grant 8,513,728 - Ghazavi , et al. August 20, 2	2013-08-20
Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates App 20130126958 - Ghazavi; Parviz ; et al.	2013-05-23

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