Ghalam; Ali Feiz Zarrin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ghalam; Ali Feiz Zarrin.The latest application filed is for "data bus duty cycle distortion compensation".

Company Profile

5.13.12

Ghalam; Ali Feiz Zarrin - Sunnyvale CA
Ghalam; Ali Feiz Zarrin - San Jose CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data bus duty cycle distortion compensation Grant 11,442,877 - Wang , et al. September 13, 2	2022-09-13
Internal clock distortion calibration using DC component offset of clock signal Grant 11,336,265 - Wang , et al. May 17, 2	2022-05-17
Data Bus Duty Cycle Distortion Compensation App 20220138120 - Wang; Guan ; et al.	2022-05-05
Internal Clock Distortion Calibration Using Dc Component Offset Of Clock Signal App 20210218388 - Wang; Guan ; et al.	2021-07-15
Internal clock distortion calibration using DC component offset of clock signal Grant 10,972,078 - Wang , et al. April 6, 2	2021-04-06
Managing Attributes Of Memory Components App 20210064278 - Rajgopal; Suresh ; et al.	2021-03-04
Internal Clock Distortion Calibration Using Dc Component Offset Of Clock Signal App 20200336135 - Wang; Guan ; et al.	2020-10-22
Internal clock distortion calibration using dc component offset of clock signal Grant 10,727,816 - Wang , et al.	2020-07-28
Apparatus And Methods For Serializing Data Output App 20200176059 - Pilolli; Luigi ; et al.	2020-06-04
Apparatus and methods for serializing data output Grant 10,658,041 - Pilolli , et al.	2020-05-19
Skew reduction of a wave pipeline in a memory device Grant 10,410,698 - Shakeri , et al. Sept	2019-09-10
Wave pipeline Grant 10,360,956 - Shakeri , et al.	2019-07-23
Internal Clock Distortion Calibration Using Dc Component Offset Of Clock Signal App 20190190501 - Wang; Guan ; et al.	2019-06-20
Wave Pipeline App 20190180802 - Shakeri; Kaveh ; et al.	2019-06-13
Wave Pipeline App 20190180801 - Shakeri; Kaveh ; et al.	2019-06-13
Internal clock distortion calibration using DC component offset of clock signal Grant 10,270,429 - Wang , et al.	2019-04-23
Apparatuses and methods for a memory die architecture including an interface memory Grant 9,710,182 - Nobunaga , et al. July 18, 2	2017-07-18
Devices and systems including enabling circuits Grant 9,401,188 - Tanzawa , et al. July 26, 2	2016-07-26
Apparatuses And Methods For A Memory Die Architecture Including An Interface Memory App 20160070504 - Nobunaga; Dean K. ; et al.	2016-03-10
Apparatuses and methods for a memory die architecture including an interface memory Grant 9,190,133 - Nobunaga , et al. November 17, 2	2015-11-17
Apparatuses And Methods For A Memory Die Architecture App 20140258619 - Nobunaga; Dean K. ; et al.	2014-09-11
Devices And Systems Including Enabling Circuits App 20140198586 - Tanzawa; Toru ; et al.	2014-07-17
Devices and systems including enabling circuits Grant 8,675,420 - Tanzawa , et al. March 18, 2	2014-03-18
Devices And Systems Including Enabling Circuits App 20120300556 - Tanzawa; Toru ; et al.	2012-11-29

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