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name:-0.013398170471191
name:-0.012795925140381
name:-0.015091896057129
Geva; Ofer Patent Filings

Geva; Ofer

Patent Applications and Registrations

Patent applications and USPTO patent grants for Geva; Ofer.The latest application filed is for "deep trench capacitor distibution".

Company Profile
12.9.12
  • Geva; Ofer - Poughkeepsie NY
  • Geva; Ofer - Petah Tikva IL
  • Geva; Ofer - Haifa IL
  • Geva; Ofer - Ramat Hasaron IL
  • Geva; Ofer - Hod Hasharon IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Deep trench capacitor distribution
Grant 11,296,093 - Regev , et al. April 5, 2
2022-04-05
Deep Trench Capacitor Distibution
App 20210272963 - REGEV; ASAF ;   et al.
2021-09-02
Out-of-context feedback hierarchical large block synthesis (HLBS) optimization
Grant 11,030,367 - Musante , et al. June 8, 2
2021-06-08
Method and system for aligning image data from a vehicle camera
Grant 10,997,737 - Geva , et al. May 4, 2
2021-05-04
Out-of-context Feedback Hierarchical Large Block Synthesis (hlbs) Optimization
App 20210073343 - Musante; Frank ;   et al.
2021-03-11
Integrated circuit design with optimized timing constraint configuration
Grant 10,831,958 - Geva , et al. November 10, 2
2020-11-10
Method And System For Aligning Image Data From A Vehicle Camera
App 20200349723 - Geva; Ofer ;   et al.
2020-11-05
Circuit generation based on zero wire load assertions
Grant 10,657,211 - Plotkin , et al.
2020-05-19
Integrated Circuit Design With Optimized Timing Constraint Configuration
App 20200104452 - GEVA; OFER ;   et al.
2020-04-02
Estimating timing convergence using assertion comparisons
Grant 10,572,613 - Geva , et al. Feb
2020-02-25
Modifying a circuit design
Grant 10,568,203 - Geva , et al. Feb
2020-02-18
Modifying a circuit design based on pre-routed top level design
Grant 10,546,092 - Geldman , et al. Ja
2020-01-28
Circuit Generation Based On Zero Wire Load Assertions
App 20190325102 - Plotkin; Limor ;   et al.
2019-10-24
Modifying A Circuit Design Based On Pre-routed Top Level Design
App 20190188351 - Geldman; Ido ;   et al.
2019-06-20
Estimating timing convergence using assertion comparisons
Grant 10,325,045 - Geva , et al.
2019-06-18
Modifying a Circuit Design
App 20180359852 - Geva; Ofer ;   et al.
2018-12-13
Modifying a Circuit Design
App 20180359851 - Geva; Ofer ;   et al.
2018-12-13
Estimating Timing Convergence Using Assertion Comparisons
App 20180341732 - Geva; Ofer ;   et al.
2018-11-29
Estimating Timing Convergence Using Assertion Comparisons
App 20180341731 - Geva; Ofer ;   et al.
2018-11-29
Chest Radiograph (cxr) Image Analysis
App 20180047158 - GEVA; Ofer ;   et al.
2018-02-15
Method And System For Designing A Memory Register
App 20080127019 - Amit; Niv ;   et al.
2008-05-29

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