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name:-0.017383098602295
name:-0.026556968688965
name:-0.0079169273376465
Gerousis; Vassilios Patent Filings

Gerousis; Vassilios

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gerousis; Vassilios.The latest application filed is for "semiconductor cell blocks having non-integer multiple of cell heights".

Company Profile
7.19.12
  • Gerousis; Vassilios - Georgetown TX
  • Gerousis; Vassilios - Liberty Hill TX
  • Gerousis; Vassilios - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
Grant 11,189,600 - Wang , et al. November 30, 2
2021-11-30
Method of forming isolation dielectrics for stacked field effect transistors (FETs)
Grant 11,158,738 - Wang , et al. October 26, 2
2021-10-26
Semiconductor Cell Blocks Having Non-integer Multiple Of Cell Heights
App 20210265334 - Gerousis; Vassilios ;   et al.
2021-08-26
Method Of Forming Sacrificial Self-aligned Features For Assisting Die-to-die And Die-to-wafer Direct Bonding
App 20210183814 - Wang; Wei-E ;   et al.
2021-06-17
Method Of Forming A Thermal Shield In A Monolithic 3-d Integrated Circuit
App 20210183729 - Wang; Wei-E ;   et al.
2021-06-17
Method of forming a thermal shield in a monolithic 3-D integrated circuit
Grant 10,971,420 - Wang , et al. April 6, 2
2021-04-06
Power distribution network using buried power rail
Grant 10,886,224 - Gerousis , et al. January 5, 2
2021-01-05
Method Of Forming Isolation Dielectrics For Stacked Field Effect Transistors (fets)
App 20200403097 - WANG; Wei-E ;   et al.
2020-12-24
Power Distribution Network Using Buried Power Rail
App 20200373241 - Gerousis; Vassilios ;   et al.
2020-11-26
Semiconductor device and method for making the same
Grant 10,811,415 - Sengupta , et al. October 20, 2
2020-10-20
Method Of Forming A Thermal Shield In A Monolithic 3-d Integrated Circuit
App 20200203247 - Wang; Wei-E ;   et al.
2020-06-25
Method Of Designing A Layout For A Semiconductor Integrated Circuit
App 20200201954 - Gerousis; Vassilios ;   et al.
2020-06-25
Semiconductor Device And Method For Making The Same
App 20200135735 - Sengupta; Rwik ;   et al.
2020-04-30
Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness
Grant 9,286,432 - Gerousis , et al. March 15, 2
2016-03-15
Orthogonal circuit element routing
Grant 9,245,076 - Gerousis , et al. January 26, 2
2016-01-26
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs
Grant 9,087,174 - Zhang , et al. July 21, 2
2015-07-21
Orthogonal Circuit Element Routing
App 20140359548 - Gerousis; Vassilios ;   et al.
2014-12-04
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design
Grant 8,863,048 - Gerousis , et al. October 14, 2
2014-10-14
Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
Grant 8,782,586 - Sezginer , et al. July 15, 2
2014-07-15
Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques
Grant 8,782,570 - Li , et al. July 15, 2
2014-07-15
Static timing analysis with design-specific on chip variation de-rating factors
Grant 8,762,908 - Chang , et al. June 24, 2
2014-06-24
Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits
Grant 8,336,010 - Chang , et al. December 18, 2
2012-12-18
System and method of computing pin criticalities under process variations for timing analysis and optimization
Grant 8,151,229 - Chang , et al. April 3, 2
2012-04-03
Method and system for performing statistical leakage characterization, analysis, and modeling
Grant 8,086,978 - Zhang , et al. December 27, 2
2011-12-27
Method and system for performing statistical leakage characterization, analysis, and modeling
Grant 8,069,432 - Zhang , et al. November 29, 2
2011-11-29
Method, System, And Program Product For Routing An Integrated Circuit To Be Manufactured By Doubled Patterning
App 20110014786 - Sezginer; Abdurrahman ;   et al.
2011-01-20
Method And System For Performing Statistical Leakage Characterization, Analysis, And Modeling
App 20100083198 - Zhang; Lizheng ;   et al.
2010-04-01
Method And System For Performing Statistical Leakage Characterization, Analysis, And Modeling
App 20090319969 - Zhang; Lizheng ;   et al.
2009-12-24

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