Gernhoefer; Veit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gernhoefer; Veit.The latest application filed is for "post timing layout modification for performance".

Company Profile

0.5.7

Gernhoefer; Veit - Holzgerlingen N/A DE
Gernhoefer; Veit - Hoizgerlingen DE
Gernhoefer; Veit - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Post timing layout modification for performance Grant 8,448,124 - Fassnacht , et al. May 21, 2	2013-05-21
Post Timing Layout Modification For Performance App 20130074025 - Fassnacht; Uwe ; et al.	2013-03-21
Layout optimization using parameterized cells Grant 7,865,848 - Gernhoefer , et al. January 4, 2	2011-01-04
Independent migration of hierarchical designs with methods of finding and fixing opens during migration Grant 7,568,173 - Gernhoefer , et al. July 28, 2	2009-07-28
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method App 20090112963 - Haller; Wilhelm ; et al.	2009-04-30
Layout Optimization Using Parameterized Cells App 20090064061 - Gernhoefer; Veit ; et al.	2009-03-05
Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration App 20080313581 - Gernhoefer; Veit ; et al.	2008-12-18
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method App 20080071852 - Haller; Wilhelm ; et al.	2008-03-20
Method and device for automated layer generation for double-gate FinFET designs Grant 7,315,994 - Aller , et al. January 1, 2	2008-01-01
Method and device for automated layer generation for double-gate FinFET designs App 20050136582 - Aller, Ingo ; et al.	2005-06-23

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