| Patent | Date |
|---|
Circuit Arrangement For Controlling A Plurality Of Electrical Loads
App 20220231505 - Gerhardt; Martin ; et al. | 2022-07-21 |
Transistor element with reduced lateral electrical field
Grant 10,580,863 - Angot , et al. | 2020-03-03 |
Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell
Grant 10,529,728 - Richter , et al. J | 2020-01-07 |
Transistor Element With Reduced Lateral Electrical Field
App 20190109192 - Angot; Damien ; et al. | 2019-04-11 |
Heat dissipative element for polysilicon resistor bank
Grant 10,256,134 - Mikalo , et al. | 2019-04-09 |
Heat Dissipative Element For Polysilicon Resistor Bank
App 20180358259 - Mikalo; Ricardo P. ; et al. | 2018-12-13 |
Semiconductor Structure Including A Plurality Of Pairs Of Nonvolatile Memory Cells And An Edge Cell
App 20180158833 - Richter; Ralf ; et al. | 2018-06-07 |
Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof
Grant 9,922,986 - Richter , et al. March 20, 2 | 2018-03-20 |
Semiconductor Structure Including A Plurality Of Pairs Of Nonvolatile Memory Cells And An Edge Cell And Method For The Formation Thereof
App 20170330889 - Richter; Ralf ; et al. | 2017-11-16 |
OPC enlarged dummy electrode to eliminate ski slope at eSiGe
Grant 9,461,145 - Yan , et al. October 4, 2 | 2016-10-04 |
Transistor devices with high-k insulation layers
Grant 9,425,194 - Gerhardt , et al. August 23, 2 | 2016-08-23 |
Opc Enlarged Dummy Electrode To Eliminate Ski Slope At Esige
App 20160099336 - YAN; Ran ; et al. | 2016-04-07 |
Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages
Grant 9,219,013 - Gerhardt , et al. December 22, 2 | 2015-12-22 |
Transistor Devices With High-k Insulation Layers
App 20150340362 - Gerhardt; Martin ; et al. | 2015-11-26 |
Methods of forming transistor devices with high-k insulation layers and the resulting devices
Grant 9,136,177 - Gerhardt , et al. September 15, 2 | 2015-09-15 |
Method for forming a strained transistor by stress memorization based on a stressed implantation mask
Grant 9,117,929 - Wirbeleit , et al. August 25, 2 | 2015-08-25 |
Technique For Manufacturing Semiconductor Devices Comprising Transistors With Different Threshold Voltages
App 20140273370 - Gerhardt; Martin ; et al. | 2014-09-18 |
Integrated Circuits Having Boron-doped Silicon Germanium Channels And Methods For Fabricating The Same
App 20140070321 - Gerhardt; Martin ; et al. | 2014-03-13 |
Methods Of Forming Transistor Devices With High-k Insulation Layers And The Resulting Devices
App 20140027859 - Gerhardt; Martin ; et al. | 2014-01-30 |
Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation
Grant 8,614,134 - Gerhardt , et al. December 24, 2 | 2013-12-24 |
Technique for enhancing transistor performance by transistor specific contact design
Grant 8,541,885 - Gerhardt , et al. September 24, 2 | 2013-09-24 |
Methods of Forming Source/Drain Regions on Transistor Devices
App 20130095627 - Flachowsky; Stefan ; et al. | 2013-04-18 |
Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy
Grant 8,349,694 - Kronholz , et al. January 8, 2 | 2013-01-08 |
Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation
App 20120241864 - Gerhardt; Martin ; et al. | 2012-09-27 |
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography
Grant 8,101,512 - Gerhardt , et al. January 24, 2 | 2012-01-24 |
Method for Forming a Strained Transistor by Stress Memorization Based on a Stressed Implantation Mask
App 20110223733 - Wirbeleit; Frank ; et al. | 2011-09-15 |
Technique for Enhancing Transistor Performance by Transistor Specific Contact Design
App 20110215415 - Gerhardt; Martin ; et al. | 2011-09-08 |
Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
Grant 7,994,059 - Richter , et al. August 9, 2 | 2011-08-09 |
Enhanced Confinement Of High-k Metal Gate Electrode Structures By Reducing Material Erosion Of A Dielectric Cap Layer Upon Forming A Strain-inducing Semiconductor Alloy
App 20110159654 - Kronholz; Stephan ; et al. | 2011-06-30 |
Method for forming a strained transistor by stress memorization based on a stressed implantation mask
Grant 7,964,458 - Wirbeleit , et al. June 21, 2 | 2011-06-21 |
Technique for enhancing transistor performance by transistor specific contact design
Grant 7,964,970 - Gerhardt , et al. June 21, 2 | 2011-06-21 |
Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region
Grant 7,871,877 - Griebenow , et al. January 18, 2 | 2011-01-18 |
Method For Fabricating A Semiconductor Device With Self-aligned Stressor And Extension Regions
App 20100047985 - DAKSHINA MURTHY; Srikanteswara ; et al. | 2010-02-25 |
Method of increasing transistor drive current by recessing an isolation trench
Grant 7,659,170 - Schwan , et al. February 9, 2 | 2010-02-09 |
Technique for transferring strain into a semiconductor region
Grant 7,494,906 - Kammler , et al. February 24, 2 | 2009-02-24 |
Methods for fabricating a stressed MOS device
Grant 7,462,524 - Peidous , et al. December 9, 2 | 2008-12-09 |
Technique For Strain Engineering In Silicon-based Transistors By Using Implantation Techniques For Forming A Strain-inducing Layer Under The Channel Region
App 20080296692 - Griebenow; Uwe ; et al. | 2008-12-04 |
Technique For Enhancing Transistor Performance By Transistor Specific Contact Design
App 20080265330 - Gerhardt; Martin ; et al. | 2008-10-30 |
Enhanced Stress Transfer In An Interlayer Dielectric By Using An Additional Stress Layer Above A Dual Stress Liner In A Semiconductor Device
App 20080179661 - Richter; Ralf ; et al. | 2008-07-31 |
Methods for fabricating a CMOS device including silicide contacts
Grant 7,348,233 - Gerhardt , et al. March 25, 2 | 2008-03-25 |
Method For Forming A Strained Transistor By Stress Memorization Based On A Stressed Implantation Mask
App 20080026572 - Wirbeleit; Frank ; et al. | 2008-01-31 |
Method Of Enhancing Lithography Capabilities During Gate Formation In Semiconductors Having A Pronounced Surface Topography
App 20080026552 - Gerhardt; Martin ; et al. | 2008-01-31 |
Method Of Increasing Transistor Drive Current By Recessing An Isolation Trench
App 20070278596 - Schwan; Christoph ; et al. | 2007-12-06 |
Method For Forming Ultra-shallow High Quality Junctions By A Combination Of Solid Phase Epitaxy And Laser Annealing
App 20070232033 - Wieczorek; Karsten ; et al. | 2007-10-04 |
Technique for transferring strain into a semiconductor region
App 20060003510 - Kammler; Thorsten ; et al. | 2006-01-05 |
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