Gerber; Donald
Patent Applications and Registrations
Patent applications and USPTO patent grants for Gerber; Donald.The latest application filed is for "method for programming and erasing an array of nmos eeprom cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits".
- Gerber; Donald - Scottsdale AZ
- Gerber, Donald - Monroe WI
| Patent | Date |
|---|---|
| Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits Grant 7,466,591 - Shields , et al. December 16, 2 | 2008-12-16 |
| Method for Programming and Erasing an Array of NMOS EEPROM Cells That Minimizes Bit Disturbances and Voltage Withstand Requirements for the Memory Array and Supporting Circuits App 20070280001 - Shields; Jeffrey A. ; et al. | 2007-12-06 |
| Independently programmable memory segments within an NMOS electrically erasable programmable read only memory array achieved by P-well separation and method therefor App 20070140008 - Shields; Jeffrey ; et al. | 2007-06-21 |
| Device for loading and unloading a load relative to a bed of a truck App 20030194304 - Davis, Kevin ; et al. | 2003-10-16 |
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