loadpatents
name:-0.0060040950775146
name:-0.0069301128387451
name:-0.0027611255645752
George; Sumitha Patent Filings

George; Sumitha

Patent Applications and Registrations

Patent applications and USPTO patent grants for George; Sumitha.The latest application filed is for "nonvolatile digital computing with ferroelectric fet".

Company Profile
5.8.7
  • George; Sumitha - State College PA
  • George; Sumitha - Bangalore IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Priority based circuit synthesis
Grant 10,678,981 - Ankenapalli , et al.
2020-06-09
Nonvolatile digital computing with ferroelectric FET
Grant 10,672,475 - Li , et al.
2020-06-02
Nonvolatile Digital Computing with Ferroelectric FET
App 20200027508 - Li; Xueqing ;   et al.
2020-01-23
Nonvolatile digital computing with ferroelectric FET
Grant 10,475,514 - Li , et al. Nov
2019-11-12
Priority Based Circuit Synthesis
App 20190034563 - Ankenapalli; Vijay K. ;   et al.
2019-01-31
Priority based circuit synthesis
Grant 10,133,840 - Ankenapalli , et al. November 20, 2
2018-11-20
Nonvolatile Digital Computing with Ferroelectric FET
App 20180330791 - Li; Xueqing ;   et al.
2018-11-15
Programmable delay circuit including hybrid fin field effect transistors (finFETs)
Grant 9,985,616 - Ankenapalli , et al. May 29, 2
2018-05-29
Priority Based Circuit Synthesis
App 20170161406 - Ankenapalli; Vijay K. ;   et al.
2017-06-08
Programmable Delay Circuit Including Hybrid Fin Field Effect Transistors (finfets)
App 20170126218 - Ankenapalli; Vijay K. ;   et al.
2017-05-04
Programmable delay circuit including hybrid fin field effect transistors (finFETs)
Grant 9,614,507 - Ankenapalli , et al. April 4, 2
2017-04-04
Programmable Delay Circuit Including Hybrid Fin Field Effect Transistors (finfets)
App 20170012615 - Ankenapalli; Vijay K. ;   et al.
2017-01-12
Programmable Delay Circuit Including Hybrid Fin Field Effect Transistors (finfets)
App 20170012616 - Ankenapalli; Vijay K. ;   et al.
2017-01-12
Programmable delay circuit including hybrid fin field effect transistors (finFETs)
Grant 9,543,935 - Ankenapalli , et al. January 10, 2
2017-01-10
Optimal spare latch selection for metal-only ECOs
Grant 8,875,084 - Ankenapalli , et al. October 28, 2
2014-10-28

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